Part Number: SN74AXC4T774
We designed a PCB with SN74AXC4T774 to convert SPI4 signals from/to 3V3(=VCCB) to/from 1V2(=VCCA) domain.
Based on SN74AXC4T774 datasheet, we would have expected MISO signal not to be delayed by more than 12ns and SCLK/CSn/MOSI signals not to be delayed by more than 7 ns.
But looking with scope we observe up to 15ns propagation delay through SN74AXC4T774 part.
In other words, when it comes to sampling MISO, we have up to 30ns delay for MISO in 3V3 domain compared to falling edge of SCLK. This is not compatible with a SPI frequency of 12MHz which is our requirement.
So can you please confirm propagation delay through SN74AXC4T774, that it is supposed to work with SPI at 12MHz ? And above all, can you please provide guidance about how to reduce this propagation delay ?
Due to the holidays, our responses are delayed. We will get back to helping you on Monday.
In the meantime, can you please provide a complete schematic of your circuit? Can you also provide scope shots of the delayed signals?
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
The values in the datasheet were measured with a load of 15 pF. Do you have long traces, cables, or connectors?
In reply to Clemens Ladisch:
Hi Karan & Clemens,
Thanks for your prompt reply.
Below is an extract of the schematics.
The SPI master is connected to green signals at 3V3. It is a Raspberry PI 3 B+ configured to output 12MHz on SCLK in SPI mode 3.
The SPI slave is connected to <name>_DB red signals at 1V2 (VDDIO = 1V2) (I2CS_DB is tied low permanently so <name>_SPI_DB are selected within TMUX). It is attached to a home made SPI slave part under test.
The trace length is very short and there is no cable at all.
To characterize SN74 part propagation delay more easily, we replaced :
I will attach scope shots of delayed signals ASAP.
In reply to Julie Gonin:
While investigating if there could be any capacitance added to the output of SN74AXC4T774 part, we finally discovered that TMUX1134 was adding capacitance to SCLK and MISO path, like explained in its datasheet. Removing TMUX1134 reduced load of the path and then we could drastically reduce propagation delay through SN74AXC4T774 part ! We are now back within datasheet timing.
Thanks a lot !
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.