I'd like to maximize the performance of my CC2430 design and therefore would like to follow exactly TI's design.
I already followed TI's reference design, related to components selection and schematic.
Now, I want to follow their PCB manufacturing, and therefore have a number of questions:
1. How many layers should the PCB have?
2. What should be the PCB's width (if it depends on the amount of layers - 2 or 4 - please specify the width for each).(in the 'CC2430+CC2591 according to swra214' I saw that you recommend 1.6mm 4-layer PCB, but i read here that you recommend 1.2mm 2-layer PCB, so i'm confused).
3. How many oz. of copper should the PCB use?
If it helps to answer the question, i'm using a single ended antenna.
Thank you very much for any help.
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Hi, Mr. Stewart.
I would like to thank you for your help throughout my CC2430 PCB design. The PCB arrived a few days ago and it worked perfectly. Without your help, I couldn't be successful for the first time.
I appreciate the feed back and I'm glad it work out well.
As the RF Engineer from TI who layouts the PCB boards I been following this Blog and most comments are correct. In terms of this layout it was designed to reduce the cost of the balun/fileter matching network. Therefoe the long traces which are part of the balun network.
The entire process of matching at high frequencies is to ensure the maximum power is delivered to the load. You can use any one of three baluns to do this. 1) discrete components 2) intergrated solution or 3) PCB strip line balun. The trade offs are cost, size and preformance. Baluns are used to take differential signals to single-ended and do the power match. Most people focus upon the power match and don't pay attention to the baluns phase summing. This takes two out phase signals and aligns them in phase so the total voltage doubles at the summing point. The impedance match is done so to match a transmission line or antennas input impedance. Often the balun output is not 50 ohms but lower value so the components values are larger for less variation in the circuit if discrete. Another important point missed is the traces which are << than quarter wavelengths act as inductors. Since the component values discrete steps are fairly large for these frequencies the traces are used to fine tune the phase by summing to the inductors in the balun. Therefore the summing point has a (real + jzero) value. The matching filter then is used to change the impedance to a transmission line characteristic impedance of 50 ohms. Most layout designers don't like to pay for controller impedance lines so they use a line calculator and come up with the width of the line that is close and rely on the board vendors tolerance to maintain the 50 ohm line. So if your product will have millions made then its safer to add another matching network between the antenna and the 50 ohm transmission line. Also often the antenna is not exactly 50 ohms so including a matching network is good design procedure to follow. You can always add zero ohm reistors if no matching is needed.
Since board stackup is a way to size the width of the boards it also can be sued on multilayer boards to keep the same impedance. By using the layer stacking and a good line calculator you can determine the reference designs line impedances and copy them to your prototype design. Then use the component values from the reference design and you most likely will have maximum power to your antenna.
TI Sr. RF Engineer
Low Power Wireless & antennas
LPW Support Group
I have a similar problem as what is being discussed in this post. I am hoping to pose my question here and have the Guru's help me figure out the path forward.
Using the CC2531 Donggle board as a starting point I removed the internal patch antenna that is specified on the Donggle reference design and copied the SMA antenna design from the CC2530-EM board reference design. In effect this means that I have married an antenna design specified for the 2 layer board to an 4 layer board. The track lengths and widths were unfortunately kept the same as specified in the 2 layer reference design. The thickness between the top layer and the first ground layer is 0.43 mm. The manufacturer states that the permittivity is 4.6 as opposed to the 4.5 specified by Ti in their reference design. I observe a loss of 14dB in receive power and 21 dB loss in transmit power as compared to the original TI reference design.
Based on my calculation and posts by folks here, here is what I understand. The original TI reference design had a line width of 1.4 mm and a thickness of 0.8mm for the 50Ohm transmission line. This gives a perfect 50-Ohm transmission line. In my case this is now 33.5 Ohms. (since my w/h ratio of 3.24).
a) Should this change in 50-Ohm transmission line cause a 14 dB loss in receive power? A simple simulation does not show that much difference. I am trying to figure out if there is some other problem in the PCB layout/design.
b) The value of the inductance L252/L261 is specified as 2nH. L252/L261 is the inductances specified in the EM board reference design swrc144a. Even after using a 50 Ohm transmission line, in a simple RF simulation using rfsim99 I am not able to get a good S11 performance with 2nH. The circuit seems to work much better with 5nH. Can someone confirm the 2nH number?
c) Is there any hope of using different matching components and regaining most of the loss in performance caused by a poor transmission line (34 Ohms?)
Thank you, Sharat
Hi Sharat, I can help with this. Bad microstrip line can have this effect. I have also seen this trash the EVM. There are two places you can loose power, the differential section between the SoC and the Balun, and the unbalanced section from the balun to the antenna feed (or connector). I doubt you can dial it back in with trim components. A re-spin with proper controls is your best bet for consistent production. Are you measuring the S11 on a network analyzer, or just the simulator? Also SMA is not a legal connector, for consumer product you should be using RPSMA, or U.FL. I have done a lot of these layouts for high-volume production. Give me a call and we can talk. firstname.lastname@example.org
If it was just 33 ohms versus 50 in the output transmission line I do not believe you would see more than a few dB at most since the line should be from the balun/matching network output and the SMA antenna connector and is only about 5mm long. What is not clear in your description is how much of each circuit design did you use. The dongle is based on a chip balun while the swrc144a design has a discrete component balun.
Sharat Anan I am not able to get a good S11 performance with 2nH
Without having the matching parameters for the CC2530 it is difficult to build a good CAD model for the circuit and it is important to note that a good power match for an active device is typically not at the lowest S11. Also with this type of design the match must be considered at several harmonics above the fundamental. RRS has a very good post directly above your post and stresses the importance of good phase balance within and feeding the balun.
I believe there is more going on here than just the dielectric thickness. While it is likely a respin for production may be required it would likely be a help to get these units up to a useful state for software development and initial testing.
A screen capture of the PCb layout from the CC2530's two output pins to the SMA connector would really help.
( a great free tool for capturing a part of the screen is screenprint32 V3 at screenprint32.com I've used it with XP Pro 32 and now with Windows 7 64 in XP compatibility mode)
a) No a 50 transmission line does not cause 14dB reciever loss. Your permittivity numbers don't seem releatistic at 2.45GHz. It looks like numbers for 1GHz. This decreases with frequency. Most board vendors in Europe quote 4.22 In US 4.11 @ 2.45GHz. The ratio with a 4.11 is about 2:1 in height to trace width for 50 ohms. So you can work at the loss if 33 ohms, but this still isn't close to 14dB. So you have other problems.
b) The balun matching requires high self resonance components. We only found certain vendors who sell these inductors so make sure you use the inductors listed for the board stackup. The summing point of the balun sums the 2 in phase signals to get 2X the signal. Measure using a spectrum analyzer the output power to the antenna. Disconnect the antenna add a piece of coax to the output and measure the power into a spectrum analyzer for a single tone at 2.45GHz. If the power is 14 dB low then the board is the problem.
If the power is OK in TX mode then you match to the antenna is subject or the antenna is now some imedance other than 50+j0. Copying Monopole antennas while not observing the correct ground plane size will change their imput impedance.
Simulation files for the microstrip lines are generally very accurate. We use Agilents ADS to design the PCB RF layout and find the accuracy is limited by the tolerance on the discrete components. We inclulde the component vendors s-parameter files for the component series so see correlation to measurements <1%. error. The components must be Muratas, do not subsitute.
Thanks for your replies. I was hoping to hear from you! I have attached a screen shot of the PCB layout
Stewart: As shown in the figure a discrete Balun was used. (The discrete Balun was copied from CC2530 design). It seems that a 14dB problem is so large, the problem should be starting me in the face. (It probably is above but I am not an RF-Antenna designer.) As you mentioned it would be good solve a host of other problems using the current boards before a respin...
RRS: Powerloss is measured in the following way (a) Use 2 TI-EB boards. Connect them with a coax wire instead of the antenna. Transmit 0dBm one one board and measure 0dBm on the other (RSSI measurement using packet sniffer). So far so good, this is now the reference. Remove one TI-EB board and use the manufactured PCB. Repeat the above experiement and measure -14dBm. That is our friendly 14dB loss. You recommended disconnecting the antenna and adding a piece of coax. Is that similar to the above experiment, or did you mean to desolder the SMA connector and then solder some wires on? You mentioned antenna ground plane. Given that the design above is using through-hole SMA instead of the surface mount SMA in the TI-EB boards, can this cause a problem?
I will recheck to see if the parts are actually Murata.
Looking at the lay out I see several thing that would kill the gain. It may be just a artifact of the layers that are shown.
Overall the component placement looks very good.
It appears the balun components are only grounded to the top copper pour and do not have vias. It also appear there are no ground vias under the device, these are critical. Micro-strip is formed by having a transmission line over a layer 2 ground plane. To function as a ground plane it must be the connect point for all of the shunt components with grounds. It is good to include the top layer copper pour as ground provided it is well attached to the layer 2 ground plane with numerous plated vias while avoiding isolated pours that serve as couplers between RF elements.
So if the components grounds are attached to the top pour only ( a via or two in the far corners do not count) and the back of the chip is isolated it is clear where the gain/power went.
A nit is the copper pour to transmission line spacing should be at least 2X the dielectric thickness. For a short (<10%) line 1 dielectric space will work. In either the case the top pour should have vias to ground spaced not more than 10% lambda so it does not become a radiating element.
As a comment layer 2 is typically a ground plane for both DC and RF, layer 3 is Vcc and the back of the board is also ground. Layer 2 can be the Vcc plane and still function as the RF ground plane provided it is very well bypassed with caps to the ground plane.
NOw you are learning about RF and transmission lines. Actually they are very easy to understand. There is an App note that discuss most of the items you are dealing with AN068. The spacing of the vais does several things.
1) It makes the ground planes the same impedance level.
2) It forces Trans Electric Mode (TEM) of board oscillation to higher frequency
3) It reduces the noise for low radio sensitivity pickup.
Once you correct your board and built new gerber files, if you send me your email, I'll instruct you where to send them to TI to have us look at your layout for mistakes and provide you with a simulation of the board. There is no charge so this will help you from spending addional money on prototype boards.
Now you are learning about RF and transmission lines.
Now you are learning about RF and transmission lines.
It is Sharat's board we are looking at.
I contributed to Compact and versions of EEsof etc in addition to MIC and MMIC technology from their beginnings and for decades reaching back to 1972. Microwave fields and waves I understand, I'm comfortable with digital design, it is software where I have a lot to learn.
Sorry I was not trying to dimension your experience. The EEsof is a good program I acutally have a copy but preferr to use ADS because they have a excelent gerber tool to import customers files. We validated their models created and see less than 1% error in simulations to lab measurements on the board. I can load configure and simulate the RF path in less than 30 mins. So if you like us to view your final layout just send your email then I reply to where to send the files.
Thank you for your replies. I will work with the circuit design engineer to understand and assimilate your responses.
You had mentioned in another post on this forum "A fine drill bit and a little thru wire between the top and ground plane in about 10 places you should recover much of the loss". Do you think the same trick would work for me to salvage the current boards. I understand that I must ensure that the back of the chip is not isolated. Additionally I need to have vias from the balun elements to the ground.
Appreciate your help.
That trick works best on two layer boards. With 4 layers it is hard to capture layer 2 which you need, and hard not to get and short layer 3 which I assume is a power plane. Also how do you get to the chip's back side pad?
There are times a re-spin is needed, this is one of them.
What are the inter planes? Is the chip's pad floating? Were you thinking of modifying the assembled board or building up a new one? Do you have access to a mill? do you have hot air reflow to remove just the chip?
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