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Brian, 

To minimize latency you have to understand what causes latency, here is a recipe for a typical CC2500/CC1101 use case.

1. MCU1 wants to send data
2. MCU1 fills FIFO with data, at SPI clock rate (<5MHz)
3. MCU1 issues command to enter TX
4. RF1 starts up the TX sequence
1. Start XTAL = 300us
2. Start RF VCO = 100us
3. Lock RF VCO to XTAL (called calibrate PLL) = 800us
4. Send Preamble = 4-8 bytes of "0101" => depending on bitrate
5. Send Sync word = 2-4 bytes => depending on bitrate
6. Send payload = depending on bitrate and size
7. Send CRC check sum
5. RF2 is in RX
1. Locks on preamble
2. Finds the Sync work -> issues a Sync word found on GPIO
3. Gets Pay load
4. Get CRC and checks against calculated CRC
5. issues "End-of-Packet" on GPIO
6. MCU2 gets interupted and starts the process of emptying the FIFO.

This process can quickly take 2-3ms to complete and therefore you will get latency. So what can be done.

1. Have both TX and RX always on (called FSTXON)
2. Have short preambles/and sync words (if too aggressive settings are chosen you will get many errors, so be careful) 
3. Make very shorts packets and fill up the FIFO after the TXON command has been send (but you have to very fast)
4. It should be possible to get the latency down to <2ms
5. However if you just need tight timing, just use the SYNC word found signal. Its comes just after the Sync word has been send which is quick.

If this is not fast enough you need to start looking at using what is called "Transparent mode" in the documentation. Here the TX and RX will modulate your signals directly as you are putting it into the chip and also it will receive the signal bit for bit. This mode of operation is difficult to use, but it gives near zero latency.

Regards,
/TA