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hi,

how long  will cc1120 send a byte, I make a test and meet some questions.

Freq:420mhz     

cc112x_DRATE2=0x63  cc112x_DRATE1=0xa9  cc112x_DRATE0=0x2a (DataRate: 4800   )
cc112x_SYNC_CFG0=0x7(sync word 11bits)
cc112x_PREAMBLE_CFG1=0x0(no preamble)
cc112x_PKT_LEN=0x01(one byte)
cc112x_PKT_CFG0=0x00(fix length)
cc112x_PKT_CFG1=0x05(with CRC RSSI LQI)
cc112x_SETTLING_CFG=0x00 (no calibration)
cc112x_IOCFG3=0x06 (Interrupt mode)

I make two time points in Interrupt Function:  T1, T2.
Asserted when sync word has been sent.   T1  //first time point
De-asserted at the end of the packet.        T2  //second time point

cc112x_Cmd_EnterRx();//before send cc1120 state RX,
cc112x_Op_SendPacket(ucTemp,1);
TIM_SetCounter(TIM2,0);//after write tx fifo , I clear timer counter,and get the following results:

T1=2968 us T2=8592us
send time consuming should be the follows?
T1=11bit/4800=2291us     
T2=(11bit(SYN)+8bit(DATA)+16bit(CRC RSSI LQI)) /4800 *1000000=7291us    
 
cc112x_PKT_CFG1=0x00(without RSSI CRC LQI)
T1=2968 us T2=5259us
send time consuming should be the follows?
T2=(11bit(SYN)+8bit(DATA)) /4800 *1000000=3958us    

16bit(CRC RSSI LQI)/4800=3333us
3333+T1(5259)=T2(8592) (this time is right)
 

I want to know how the diff time is generated?here is the other test result:
 
datarate 1200
T1=11717 T2=34217 //11bit syn with CRC  
T1=11717 T2=20884 //11bit syn without CRC  
T1=15883 T2=25050 //16bit syn without CRC  

datarate 2400
T1=5884 T2=17134 //11bit syn with CRC  
T1=5884 T2=10467 //11bit syn without CRC  
T1=7967 T2=12551 //16bit syn without CRC  

datarate 9600
T1=1509 T2=4322 //11bit syn with CRC  
T1=1509 T2=2655 //11bit syn without CRC  
T1=2030 T2=3176 //16bit syn without CRC  
 
void cc112x_Op_SendPacket(uint8_t *txBuffer, uint8_t size)
{
 cc112x_Cmd_WriteTxFifo(txBuffer,size);
 cc112x_Cmd_CmdStrobe(cc112x_STX); 
}

this is my para setting

{0x06,cc112x_IOCFG3}, //                   GPIO0 IO pin configuration register.
{0x3C,cc112x_SYNC3}, //                  Sync word programming (31:24).
{0xC3,cc112x_SYNC2}, //                  Sync word programming (23:16).
{0xA5,cc112x_SYNC1}, //                  Sync word programming (15:8).
{0x5A,cc112x_SYNC0}, //                  Sync word programming (7:0).
{0x0B,cc112x_SYNC_CFG1}, //              Sync Word Detection Programming
{0x17,cc112x_SYNC_CFG0}, //              Sync Word Length Programming
{0x06,cc112x_DEVIATION_M}, //            Frequency Deviation Programming
{0x03,cc112x_MODCFG_DEV_E}, //           Modulation Format and Frequency Deviation Programming
{0x1C,cc112x_DCFILT_CFG}, //                  Digital DC removal Programming
{0x00,cc112x_PREAMBLE_CFG1}, //          Preamble Length Programming
{0x00,cc112x_PREAMBLE_CFG0}, //          Preamble Detection Programming
{0x40,cc112x_FREQ_IF_CFG}, //                 RX Mixer Frequency Programming
{0xC6,cc112x_IQIC}, //                           Digital Image Channel Compensation Programming
{0x14,cc112x_CHAN_BW}, //                 Channel Filter Programming
{0x46,cc112x_MDMCFG1}, //                General Modem Parameter register.
{0x05,cc112x_MDMCFG0}, //                General Modem Parameter register.
{0x43,cc112x_DRATE2}, //                     Symbol Rate Programming Exponent and Mantissa (19:16).
{0xA9,cc112x_DRATE1}, //                     Symbol Rate Programming Mantissa (15:8).
{0x2A,cc112x_DRATE0}, //                     Symbol Rate Programming Mantissa (7:0).
{0x20,cc112x_AGC_REF}, //                    AGC Reference Level
{0x19,cc112x_AGC_CS_THR}, //             Carrier Sense Threshold Programming
{0x00,cc112x_AGC_GAIN_ADJUST},//    RSSI Offset Programming.
{0x91,cc112x_AGC_CFG3}, //                 AGC Programming
{0x20,cc112x_AGC_CFG2}, //                 AGC Programming.
{0xA9,cc112x_AGC_CFG1}, //                 AGC Programming
{0xCF,cc112x_AGC_CFG0}, //                 AGC Programming
{0x00,cc112x_FIFO_CFG}, //    
{0x00,cc112x_DEV_ADDR}, // 
{0x00,cc112x_SETTLING_CFG},
//820.0 - 960.0 MHz band (LO divider = 4)
//410.0 - 480.0 MHz band (LO divider = 8)
//273.3 - 320.0 MHz band (LO divider = 12)
//205.0 - 240.0 MHz band (LO divider = 16)
//164.0 - 192.0 MHz band (LO divider = 20)
//136.7 - 160.0 MHz band (LO divider = 24)         
{0x14,cc112x_FS_CFG}, //410.0 - 480.0        
//{0x08,cc112x_WOR_CFG1}, //              
//{0x21,cc112x_WOR_CFG0}, //              
//{0x00,cc112x_WOR_EVENT0_MSB}, //        
//{0x00,cc112x_WOR_EVENT0_LSB}, //
{0x00,cc112x_PKT_CFG2}, //    
{0x05,cc112x_PKT_CFG1}, //              
{0x00,cc112x_PKT_CFG0}, //   
{0x0F,cc112x_RFEND_CFG1}, //            
{0x00,cc112x_RFEND_CFG0}, //     
{0x7F,cc112x_PA_CFG2}, //                Power Amplifier Level Programming
{0x56,cc112x_PA_CFG1}, //                Power Amplifier Ramp Up/Down Shape Programming
{0x7C,cc112x_PA_CFG0}, //  
{0x1,cc112x_PKT_LEN}, //     
{0x00,cc112x_IF_MIX_CFG}, //                IF MIX configuration
{0x22,cc112x_FREQOFF_CFG}, //            Frequency Offset Removal programming.
{0x0B,cc112x_TOC_CFG}, //                    Data Rate Offset Removal Programming
{0x00,cc112x_SOFT_TX_DATA_CFG}, //      
{0x6C,cc112x_FREQ2}, //                 
{0x80,cc112x_FREQ1}, //                
{0x00,cc112x_FREQ0}, //        
/*        
{0x02,cc112x_IF_ADC2}, //                Analog to digital converter, reg 2
{0xA6,cc112x_IF_ADC1}, //                Analog to digital converter, reg 1
{0x04,cc112x_IF_ADC0}, //                Analog to digital converter, reg 0
*/
{0x00,cc112x_FS_DIG1}, //   
{0x5F,cc112x_FS_DIG0}, //     
//{0x00,cc112x_FS_CAL3}, //      
//{0x20,cc112x_FS_CAL2}, //               
//{0x40,cc112x_FS_CAL1}, //  
{0x0E,cc112x_FS_CAL0}, //              
//{0x28,cc112x_FS_CHP}, //                  Charge Pump Current and Calibration. Use values from SmartRF Studio
{0x03,cc112x_FS_DIVTWO}, //              Divide by 2
//{0x00,cc112x_FS_DSM1}, //                  Digital synthesizer module, reg 1
{0x33,cc112x_FS_DSM0}, //                  Digital synthesizer module, reg 0
//{0xFF,cc112x_FS_DVC1}, //                   Divider chain, reg 1
{0x17,cc112x_FS_DVC0}, //                   Divider chain, reg 0
{0x50,cc112x_FS_PFD}, //                      Phase-frequency detector
{0x6E,cc112x_FS_PRE}, //                      Prescaler
{0x14,cc112x_FS_REG_DIV_CML}, //        
{0xAC,cc112x_FS_SPARE}, //              
{0x0E,cc112x_XOSC5}, //                  Crystal oscillator, reg 5
{0xA0,cc112x_XOSC4}, //                  Crystal oscillator, reg 4
{0x03,cc112x_XOSC3}, //                  Crystal oscillator, reg 3
//{0x04,cc112x_XOSC2}, //                  Crystal oscillator, reg 2
{0x03,cc112x_XOSC1}, //                  Crystal oscillator, reg 1
//{0x00,cc112x_XOSC0}, //                  Crystal oscillator, reg 0
{0x00,cc112x_ANALOG_SPARE}, //