We have a problem with the CC1101 that the GDO pin configured for sync start / packet end (GDOxCFG 0x06).Sometimes the GDO pin gets asserted and deasserted while the cc1101 is in RX mode, but no detection of RSSI value (GDOxCFG 0x0E) is indicated on the other GDO pin.
The CC1101 is configured to have two GDO pinsGDO0 to assert when sync word has been sent / received, and de-asserts at the end of the packet.GDO2 for Carrier sense. High if RSSI level is above threshold. Cleared when entering IDLE mode.
We are sure that the CC1101 is in RX mode, the GDO0 toggle is not a TX packet.
Is this a known problem or have we configured the radio incorrectly?
Grateful for answers that can help us.
The following part is taken from the apps note (http://www.ti.com/lit/an/swra121a/swra121a.pdf ):
3 IOCFGx = 0x06..... The GDOx pin is asserted when a sync word has been sent / received, and de-asserted at the end of the packet. In RX, the pin will de-assert when address filtering or maximum length filtering leads to a packet being discarded or if the RX FIFO overflows.
The reason that you see GDO0 pin asserted and de-asserted without RSSI indication on GDO2 may be due to the packet being discarded for one or the other reasons mentioned.
For better understanding RSSI update and timing: http://www.ti.com/litv/pdf/swra114d
Make sure you use a 4 byte sync word as this will reduce the likelihood of false sync word detection compared to using 2 bytes sync word.
If you use 2 bytes sync word you will get a false sync word detection within seconds (unless you gate sync word detection with carrier sense).
Thank you for the replies,
To Sverre,Yes the sync word detection is set to 30/32 bits (SYNC_MODE = 3).
Pre-amble is also set to 6 bytes to get time to read the RSSI value and set the attenuation (for close-in reception DN010 ).This is the main reason we have an IRQ connected to the GDO2 with RSSI detection.
To MRC,“The reason that you see GDO0 pin asserted and de-asserted without RSSI indication on GDO2 may be due to the packet being discarded for one or the other reasonsmentioned.”
Wouldn’t the RSSI on GDO2 occur during pre-amble? Or have we misunderstood something?
I use GDO0 to interrupt when syncword is sent (L->H), and when packet is completed (H->L) (so both edges), and have seen the trailing edge to appear first (which in my interrupt I would take as an error leading to a retry. Obviously, the GDO0 pin was H before I started the packet transmission, where I expected it to be L.
Now from reading here this is appearantly due to the chip being in RX mode (as I use CCA) before transmitting the packet, and dependent on what was received during the CCA the status of the GDO0 pin may end up being H or L.
So we need to assure that the GDO0 pin is L before entering TX. That way the Interrupt performs as expected, sync word transmitted at leading edge of GDO0 pin, and packet completed at trailing edge of GDO0.
TI may want to address an application note to this usage of the GDO0 pin as I expect it to be quite common, and it is easily overlooked.
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