Hi,
Is it correctly understood that the only difference between the GPIO signals TXFIFO_THR and TXFIFO_THR_PKT is that the assert is made by filling above (127-fifo_thr) and full TX_FIFO (127bytes) respectively. By naming I would have assumed that the TXFIFO_THR_PKT signal should also take packets maybe end of this into consideration?
I'm trying to implement a system that may send above 127 bytes and do not want to block code execution while transmitting. So I need interrupts and preferably only one due to limited GPIOs on MCU.
My approach would be to use TXFIFO_THR in this way:
Let's say I want to transmit 200 bytes.
1. I fill the TX FIFO with 127 bytes, then set FIFO_CFG.FIFO_THR = 95 (127-95 as I want the interrupt eg. when TX FIFO has 32bytes left. Then I stobe TX
2. TXFIFO_THR should now be deasserted when TX FIFO has below 32 bytes left. Then I set FIFO_CFG.FIFO_THR = 127. (127-127) Because I want an interrupt when the packet is transmitted. Then I put the last 73 bytes in TX FIFO
3. Question is, will I get TXFIFO_THR deassertion or should FIFO_CFG.FIFO_THR be set to 126 instead of 127?
Do you have a better solution bearing in mind that I really only want to use one GPIO for the TX part? I have already used RX_FIFO_THR_PKT for the RX part and understand PKT_SYNC_RXTX can be used to signal end of packets, but this may not be suitable as I run with packets larger than FIFO bufer.
/Anders
