Hi All,
I trying to implement wake on radio feature with CC1101. I am using MSP430G2553 controller and to configure the CC1101 for Wake on Radio feature code is as below
#ifdef WORvoid wake_on_radio(void){ wor_init(); wor_start();}void wor_start(void){ TI_CC_SPIWriteReg(TI_CCxxx0_MCSM2, 0x02); TI_CC_SPIStrobe(TI_CCxxx0_SWORRST); TI_CC_SPIStrobe(TI_CCxxx0_SWOR);}void wor_init(void){ TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT1, 0x28); TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT0, 0xA0); TI_CC_SPIWriteReg(TI_CCxxx0_WORCTRL, 0x78); TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0, 0x18); TI_CC_SPIWriteReg(TI_CCxxx0_MCSM2, 0x01); TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0, 0x06);}
I am able to receive data with this code but not always. when transmit several times from other end , i can receive few packets only.
Please guide me if i missing something in this configuration.
Harshal
Hi
With your configuration the radio wakes up every 325 ms and stays awake for 10.17 ms before going back to SLEEP. As I do not know anything about your packet format or data rate I can only give you a general explanation. Consider the following:
Packet format: 4 bytes preamble, 4 bytes sync, 10 bytes payload, 2 bytes CRC
Data rate = 1.2 kbps
It takes ((4 + 4 + 10 + 2)*8)/1200 = 133 ms to send a packet (53.3 ms to send preamble and sync)
Data rate = 250 kbps
It takes 160/250000 = 640 us to send the same packet (256 us to send preamble and sync)
If your transmitter sends a packet at a given interval and this interval is equal to tEVENT0 (325 ms) and your transmitter and receiver are in sync you should be able to receive the packets at 250 kbps (as you are long enough in RX to receive preamble and sync) but you will not be able to detect sync at 1.2 kbps.
If your transmitter transmits at random intervals you will only receive the packets that are sent when your receiver is up and listen (you will not be able to detect preamble and sync at 1.2 kbps as your RX timeout is too short).
BR
Siri
Hello Siri,
Thanks for calculation and explanation in detail about timings. My packet format is as below
4 bytes preamble, 4 bytes sync, 1 byte of payload (+1 byte of address of receiver) and 2 CRC bytes with data rate of 250Kbps. So according to calculation I should not miss any packet which is transmitted by transmitter(Packet transmission is random, on key press event) . I tried below setting also but the result is same. Can you please guide me more to rectify the issue? And also can you please guide for easy calculation of Event 1 and Event 0 timings?
TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT1, 0xFF);TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT0, 0xFA);
With Regards,
With your settings and packet format the chance to miss a packet is great. Your tEvent0 is 300 ms and you are in RX for 9.37 ms (my calculation in the previous e-mail was wrong as I was looking in the CC430 data sheet). Transmitting a packet only takes 0.38 ms so there is a pretty big chance that your radio will be in SLEEP while your transmitter is transmitting (your radio sleeps about 97% of the time). You must wake up often enough so that you are guaranteed to receive your preamble and sync word. A solution is to either increase your preamble on the transmitter and use the RX_TIME_QUAL feature or transmit the packet several times when the button is pushed. You will also need to decrease tEvent0
I tried RX_TIME_QUAL feature and transmitted packet several times but result is same. Then i tried out below steps to improve the performance but not able to achieve the functionality
- Changed data to 1200, 4800 and 9600
- changed tEVENT0 to 14.6 ms and 50 ms
Can you please guide me for relationship between tEVENT0 and TX frame length, should it be more that transmission time or less?
Hello Siri
Just adding to above post
Also i increased preamble from 4 to 8 which again increased my packet length.
Hi Harshal
The radio needs about 4 bytes of preamble to be able to detect the sync word. If you send 8 bytes of preamble, the radio needs to wake up at an interval equal to the duration of 4 bytes. This way it will still be able to detect the preamble the next time it wakes up even if he just missed it. You have to account for the time it takes to wake up the chip and get the crystal ready (also have in mind that calibration of the PLL takes some time). I have tried to make a figure to make it easier to understand how WOR works.
4048.WOR.pdf
Hi Siri,
I tried with 8 preambles and even lower down the RF data rate to 1200. Even then also i m not able to communicate on regular basis then I monitored EVENT0 on GDO0 Pin and my observation is i cannot see repeated signal on GDO0 pin. Suppose my EVENT0 is 50 ms then i should be able too see pulse on GDO0 each after 50 ms but that is not happening. I could see the signal only one time. I cannot see the multiple pulses, I think EVENT0 is not executing the way it should. What could be the reason for it? One more thing can you please guide me more on EVENT1 timimgs?
If you can send me your register settings I will take a look at them. You must remember to set the RX Timeout to something else than "until end of packet" or else the radio will not get back to SLEEP again automatically. Also, you must remember that if a sync word is found, the radio will not go back to SLEEP automatically, but will need to have an SWOR strobe again.
Thanks for the reply.
Kindly note below settings .
Initial settings with Baud rate of 250KBPS
//settings for RF @ 868MHZ#if TI_CC_RF_FREQ == 868 // 868 MHz// Product = CC1100// Crystal accuracy = 40 ppm// X-tal frequency = 26 MHz// RF output power = 0 dBm// RX filterbandwidth = 540.000000 kHz// Deviation = 0.000000// Return state: Return to RX state upon leaving either TX or RX// Datarate = 250.000000 kbps// Modulation = (7) MSK// Manchester enable = (0) Manchester disabled// RF Frequency = 868.000000 MHz// Channel spacing = 199.951172 kHz// Channel number = 0// Optimization = Sensitivity// Sync mode = (3) 30/32 sync word bits detected// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled// Forward Error Correction = (0) FEC disabled// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.// Packetlength = 255// Preamble count = (2) 4 bytes// Append status = 1// Address check = (0) No address check// FIFO autoflush = 0// Device address = 0// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet// GDO2 signal selection = (11) Serial Clockvoid writeRFSettings(void){ // Write register settings TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2, 0x0B); // GDO2 output pin config. TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0, 0x06); // GDO0 output pin config. TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN, 0xFF); // Packet length. TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05); // Packet automation control. TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control. TI_CC_SPIWriteReg(TI_CCxxx0_ADDR, 0x20); // Device address. TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR, 0x00); // Channel number. TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1, 0x0B); // Freq synthesizer control. TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0, 0x00); // Freq synthesizer control. TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2, 0x21); // Freq control word, high byte TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1, 0x62); // Freq control word, mid byte. TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0, 0x76); // Freq control word, low byte. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4, 0x2D); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3, 0x3B); // Modem configuration.
// TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4, 0x27); // Modem configuration.// TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3, 0x83); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2, 0x73); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1, 0x22); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0, 0xF8); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN, 0x00); // Modem dev (when FSK mod en) TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 , 0x3F); //MainRadio Cntrl State Machine TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 , 0x18); //MainRadio Cntrl State Machine TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG, 0x1D); // Freq Offset Compens. Config TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG, 0x1C); // Bit synchronization config. TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control. TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control. TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control. TI_CC_SPIWriteReg(TI_CCxxx0_FREND1, 0xB6); // Front end RX configuration. TI_CC_SPIWriteReg(TI_CCxxx0_FREND0, 0x10); // Front end RX configuration. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3, 0xEA); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2, 0x0A); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1, 0x00); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0, 0x11); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST, 0x59); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_TEST2, 0x88); // Various test settings. TI_CC_SPIWriteReg(TI_CCxxx0_TEST1, 0x31); // Various test settings. TI_CC_SPIWriteReg(TI_CCxxx0_TEST0, 0x0B); // Various test settings.}
Then I changes RF Data rate to 1200 , I had copied this settings from Smart RF studio.
TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2, 0x0B); // GDO2 output pin config. TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0, 0x06); // GDO0 output pin config. TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN, 0xFF); // Packet length. TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05); // Packet automation control. TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control. TI_CC_SPIWriteReg(TI_CCxxx0_ADDR, 0x01); // Device address. TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR, 0x00); // Channel number. TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1, 0x06); // Freq synthesizer control. TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0, 0x00); // Freq synthesizer control. TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2, 0x21); // Freq control word, high byte TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1, 0x62); // Freq control word, mid byte. TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0, 0x76); // Freq control word, low byte. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4, 0xF5); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3, 0x83); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2, 0x93); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1, 0x42); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0, 0xF8); // Modem configuration. TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN, 0x15); // Modem dev (when FSK mod en) TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 , 0x3F); //MainRadio Cntrl State Machine TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 , 0x18); //MainRadio Cntrl State Machine TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG, 0x16); // Freq Offset Compens. Config TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG, 0x1C); // Bit synchronization config. TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control. TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control. TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control. TI_CC_SPIWriteReg(TI_CCxxx0_FREND1, 0xB6); // Front end RX configuration. TI_CC_SPIWriteReg(TI_CCxxx0_FREND0, 0x10); // Front end RX configuration. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3, 0xE9); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2, 0x2A); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1, 0x1F); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0, 0x11); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST, 0x59); // Frequency synthesizer cal. TI_CC_SPIWriteReg(TI_CCxxx0_TEST2, 0x81); // Various test settings. TI_CC_SPIWriteReg(TI_CCxxx0_TEST1, 0x35); // Various test settings. TI_CC_SPIWriteReg(TI_CCxxx0_TEST0, 0x09); // Various test settings.
Settings for the WOR
void wor_start(void){ //TI_CC_SPIWriteReg(TI_CCxxx0_MCSM2, 0x00); TI_CC_SPIStrobe(TI_CCxxx0_SWORRST); TI_CC_SPIStrobe(TI_CCxxx0_SWOR);}void wor_init(void){ TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT1, 0xF1); TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT0, 0x01); TI_CC_SPIWriteReg(TI_CCxxx0_WORCTRL, 0x78); TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0, 0x18); TI_CC_SPIWriteReg(TI_CCxxx0_MCSM2, 0x01); TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0, 0x24); TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2, 0x25);}
For Event0 i tried out various timings of 50 ms , 100ms and 300ms.
Please see the attachment.
7115.WOR_example.pdf
Thanks for the document and link. I will try this at my end will late you know.
Thanks for the settings. I tested these with 868MHz. Module is going to sleep mode and receiving data on each time.