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CC2538 RF4CE

Other Parts Discussed in Thread: CC2538, CC2530, CC2650

Hi,

is it available RF4CE stack for the new product CC2538 or I have to use CC2530?

 

Best Regards,

Roberto

  • Hi Roberto,

    CC2538 is considered a little overkill for a typical RF4CE application. As such the stack is not yet available on this platform. Would you please elaborate on your use case?

  • Hi Torbjorn,

    We are considering to use CC2538 for a remote control as well. It is a smart device with many features that needs to generate IR codes as well.

    We have successfully tested it on the CC2530, but failed on the CC2538. 

    Is it possible to generate IR codes using CC2538?

    Regards,

    Ran.

  • Hi Ran,

    The IR generation sample code we have for CC25xx won't work on CC2538 since the core is ARM Cortex M3 and the peripherals are different. However, I did some investigation and it is absolutely possible, and you can even get better resolution and more flexibility.

    CC2538 IR code generation 

    IR code generation, for CC2538, cannot be generated using the same method as described in the section 9.9 of the CC253x user guide.  This is due to a limitation of the GPT IP in PWM mode.   It is however possible to generate IR codes using an alternate timer configuration.

    Using two GPTs,  GPT0A is used to generate the carrier signal, with it’s pwm output.  The 2nd timer, GPT0B, generates pwm for the modulation signal.  GPT0B uses the same clock and starts synchronously with the first timer.  Both timers are configured for PWM mode with a period equal to some integer multiple of the number of timer ticks in the timer 1 (carrier) period. The DMA is used to write registers in the timers.  When the modulation signal falling edge occurs (end of the mark period), a DMA trigger is generated by GPT0B.  At that time, in this example, the DMA uses two channels: one to write the ILR, and one for the Match register of GPT0B.  One DMA channel is dedicated for each register.  This way the channels can be programmed one time by the cpu to handle an entire sequence of IR-codes.  Each trigger from the GPT0B will cause each channel to update one register with one value. So, each trigger will preload values for the next modulation cycle length and mark length (see the diagram below).  It is possible to extend this to also include updating of any other GPT register, for instance the pre-scale register, by adding another DMA channel, and programming the Event Fabric to route the trigger to that channel. 

     

    The limitation to using the hardware triggers, as described above, is that there are only a maximum of 5 programmable DMA channels in the CC2538.  An alternative to hardware triggers is to use software triggering.  When using software triggering only one DMA channel needs to use a hardware trigger.  That channel is then programmed to write data to the software trigger register in the uDMA.  The software trigger reg can in turn generate triggers to any of the other 31 DMA channels, providing more channel resources than the five hardware programmable channels.

     

    For the above example the sequence of events follows:

    1. the cpu configures DMA ch A and ch B to write one word for each trigger received
    1. Ch A is data is configured as a series of values to write to the interval load register (ILR) in GPT 0B.  This controls the length of the modulation cycle by specifying the number of clock ticks need.  The DMA will provide its 1st data starting at the 2nd IR-code
    2. Ch B data consists of a series of words written to the GPT 0B Match register.  This specifies the length of the mark time for each modulation cycle.  This also starts with data for the 2nd IR-code
    • GPT 0A is programmed, by the cpu, for pwm mode to produce the carrier signal
    • GPT 0B is programmed, by the cpu, for pwm mode with data for the 1st IR-code.  GPT 0B is also programmed to generate a DMA trigger on match, and an interrupt when dma_done is received from the uDMA
    • The ccp AND register is programmed to AND the pwm outputs together for GPT 0A and 0B.
    • An interrupt routine is configured to handle the dma_done interrupt for the completion of the entire sequence.
    • To get it started the GPT 0A and 0B are enabled.
    • The sequence is handled by the DMA and GPT until the DMA transfers are completed.  This happens after the last word is written for the DMA for the last IR-code.
    • An interrupt is generated to the CPU which can set-up another sequence or stop.

     

    EXAMPLE 2:

    An addition to the above implementation, example 2 also shows one way for changing the carrier signal at any time during any or all modulation cycles.  The example below also explains the use of software triggers. 

     

    This is becomes fairly complex as this example uses eight DMA channels:

    1. modulator signal cycle length (same as above example except triggered by software)
    2. modulator mark length (same as above example except triggered by software)
    3. Ch A – hardware triggered by GPT0B to trigger SW transfers
    4. Ch B – hardware triggered by GPT1A to trigger SW transfers
    5. software triggered ch to load GPT0A ILR for carrier
    6. software triggered ch to load GPT0A Match reg for carrier
    7. software triggered ch to load GPT1A ILR for controlling carrier freq change
    8. software triggered ch to load GPT1A Match reg for controlling carrier freq change

     

    In this example the carrier frequency can change in two places; a new value can be programmed at the beginning of the IR-code, or can be programmed at any time during the mark period.  Four additional DMA channels are needed to support the carrier frequency change; one channel for the ILR load of GPT1A and one for the Match load of GPT 1A, one for the ILR of GPT 0A (carrier) and one for the Match load of GPT 0A.  To control the change at the beginning of the IR-Code a  trigger is generated at the end of the mark time using GPT0B, This will spark transfers on four channels to load ILR and Match registers for both GPT0B and 1A.  To control a change of carrier frequency during the mark period, a timer 1A match event generates a trigger.  This trigger will  be used to reload the ILR and Match reg of GPT 0A.  The match value controls the point in time to adjust the carier frequency and should be applied at the end of the desired carrier pulse.  In the diagram below after four carrier pulses the GPT 1A changes the freq.

     

    To trigger software transfers, a write to the uDMA SW Request register is required.  The register has one bit for triggering each channel.  To make use of the feature, the desired channel(s) must be setup and enabled by the cpu.  Then writing to the SW request reg with the correct bit or bits set will trigger the desired channel(s).  In this discussion the channels are assumed to be set up in BASIC mode, which will transfer one word for each trigger.

     

    A write to the SW Request register can be done by the cpu or by the DMA itself.  In this example there are two points in the IR-code cycle that need to be used for writing values into the timer registers.  The first point is at the end of the mark time (refer to the diagram below).  This time is indicated by the dma trigger output of GPT0B.  The second point is the carrier frequency change point (during the mark period).  This time is indicated by a dma trigger output from GPT1A.  In both cases the GPT trigger outputs are used to trigger a dma channel.  Those channels are then used to write the DMA SW Request register, which will trigger software transfers on multiple DMA channels. The software transfers are then used to load the needed timer registers.  The software triggers are used because there are a limited number of timer hardware triggers.

      

     

    For the above example the sequence of events follows:

    1. The cpu configures all needed DMA channels (see the above list), one word for each trigger received
    2. The CPU writes to the DMA SW Request register to trigger six software dma transfers to load the initial values in all three timers, this is one word for each of six channels to load the ILR and Match registers.  All three timers are programmed for pwm mode
    1. GPT 0B is programmed to generate a DMA trigger on match (end for mark), and an interrupt when dma_done is received from the uDMA
    2. GPT 1A is programmed to generate a DMA trigger on match (carier freq change)
    • The ccp AND register is programmed to AND the pwm outputs together for GPT 0A and 0B.
    • An interrupt routine is configured to handle the dma_done interrupt for the completion of the entire sequence.
    • To get it started the GPT 0A, 0B, and 1A are enabled.  The sequence is handled by the DMA and GPTs until the DMA transfers are completed.  This happens after the last word is written for the DMA for the last IR-code.
    • The timers start counting.
    • The first event occurs when a GPT1A match generates a DMA trigger for the purpose of changing the carrier frequency during the mark period of the  IR-code.
    • The trigger causes a DMA transfer of one word to the DMA SW Request register.
    • The write to the DMA SW Request register triggers two DMA transfers, on two different channels, to write the ILR and Match register for GPT0A.  When the timer counts to zero the new values are loaded; this changes the carrier frequency.
    • The next event occurs on a timer 0B match.  This will generate a trigger for the purpose of changing the modulation signal and the the carrier frequency at the beginning of the next IR-code.
    • The trigger causes a DMA transfer of one word to the DMA SW Request Register.
    • The write to the DMA SW Request register triggers six DMA transfers, on six different channels, to write the ILR and Match register for GPTs 0A, 0B, and 1A.  When the timers count to zero the new values are loaded; this changes modulation cycle length, the modulation mark length, and the carrier frequency.
    • Steps 7 through 12 are repeated for each IR-code until all are complete and a dma_done is generated.
    • A dma_done interrupt is generated to the CPU which can set-up another sequence or stop.

     

    Note: It is straight forward to include updates to other GPT registers like pre-scale, by adding another DMA channel per register to the above example.

  • Hi ,

    I tried to follow your example and i've a few questions :


    Is the CC2538 able to generate a DMA trigger with the GPT ?

    Is the CC2538 able to AND GPTA and GPTB ?

    i don't know if it's possibe to do this with the CC2538 i was searching the user guide and i finded

    nothing relevant.

    thanks in advance,

    Victor Roselló.

  • hi:

          Do you have the sample code of  IR generation by using the cc2650? Can you share it?