Hi,
is it available RF4CE stack for the new product CC2538 or I have to use CC2530?
Best Regards,
Roberto
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Hi Roberto,
CC2538 is considered a little overkill for a typical RF4CE application. As such the stack is not yet available on this platform. Would you please elaborate on your use case?
Hi Torbjorn,
We are considering to use CC2538 for a remote control as well. It is a smart device with many features that needs to generate IR codes as well.
We have successfully tested it on the CC2530, but failed on the CC2538.
Is it possible to generate IR codes using CC2538?
Regards,
Ran.
Hi Ran,
The IR generation sample code we have for CC25xx won't work on CC2538 since the core is ARM Cortex M3 and the peripherals are different. However, I did some investigation and it is absolutely possible, and you can even get better resolution and more flexibility.
CC2538 IR code generation
IR code generation, for CC2538, cannot be generated using the same method as described in the section 9.9 of the CC253x user guide. This is due to a limitation of the GPT IP in PWM mode. It is however possible to generate IR codes using an alternate timer configuration.
Using two GPTs, GPT0A is used to generate the carrier signal, with it’s pwm output. The 2nd timer, GPT0B, generates pwm for the modulation signal. GPT0B uses the same clock and starts synchronously with the first timer. Both timers are configured for PWM mode with a period equal to some integer multiple of the number of timer ticks in the timer 1 (carrier) period. The DMA is used to write registers in the timers. When the modulation signal falling edge occurs (end of the mark period), a DMA trigger is generated by GPT0B. At that time, in this example, the DMA uses two channels: one to write the ILR, and one for the Match register of GPT0B. One DMA channel is dedicated for each register. This way the channels can be programmed one time by the cpu to handle an entire sequence of IR-codes. Each trigger from the GPT0B will cause each channel to update one register with one value. So, each trigger will preload values for the next modulation cycle length and mark length (see the diagram below). It is possible to extend this to also include updating of any other GPT register, for instance the pre-scale register, by adding another DMA channel, and programming the Event Fabric to route the trigger to that channel.
The limitation to using the hardware triggers, as described above, is that there are only a maximum of 5 programmable DMA channels in the CC2538. An alternative to hardware triggers is to use software triggering. When using software triggering only one DMA channel needs to use a hardware trigger. That channel is then programmed to write data to the software trigger register in the uDMA. The software trigger reg can in turn generate triggers to any of the other 31 DMA channels, providing more channel resources than the five hardware programmable channels.
For the above example the sequence of events follows:
EXAMPLE 2:
An addition to the above implementation, example 2 also shows one way for changing the carrier signal at any time during any or all modulation cycles. The example below also explains the use of software triggers.
This is becomes fairly complex as this example uses eight DMA channels:
In this example the carrier frequency can change in two places; a new value can be programmed at the beginning of the IR-code, or can be programmed at any time during the mark period. Four additional DMA channels are needed to support the carrier frequency change; one channel for the ILR load of GPT1A and one for the Match load of GPT 1A, one for the ILR of GPT 0A (carrier) and one for the Match load of GPT 0A. To control the change at the beginning of the IR-Code a trigger is generated at the end of the mark time using GPT0B, This will spark transfers on four channels to load ILR and Match registers for both GPT0B and 1A. To control a change of carrier frequency during the mark period, a timer 1A match event generates a trigger. This trigger will be used to reload the ILR and Match reg of GPT 0A. The match value controls the point in time to adjust the carier frequency and should be applied at the end of the desired carrier pulse. In the diagram below after four carrier pulses the GPT 1A changes the freq.
To trigger software transfers, a write to the uDMA SW Request register is required. The register has one bit for triggering each channel. To make use of the feature, the desired channel(s) must be setup and enabled by the cpu. Then writing to the SW request reg with the correct bit or bits set will trigger the desired channel(s). In this discussion the channels are assumed to be set up in BASIC mode, which will transfer one word for each trigger.
A write to the SW Request register can be done by the cpu or by the DMA itself. In this example there are two points in the IR-code cycle that need to be used for writing values into the timer registers. The first point is at the end of the mark time (refer to the diagram below). This time is indicated by the dma trigger output of GPT0B. The second point is the carrier frequency change point (during the mark period). This time is indicated by a dma trigger output from GPT1A. In both cases the GPT trigger outputs are used to trigger a dma channel. Those channels are then used to write the DMA SW Request register, which will trigger software transfers on multiple DMA channels. The software transfers are then used to load the needed timer registers. The software triggers are used because there are a limited number of timer hardware triggers.
For the above example the sequence of events follows:
Note: It is straight forward to include updates to other GPT registers like pre-scale, by adding another DMA channel per register to the above example.
Hi ,
I tried to follow your example and i've a few questions :
Is the CC2538 able to generate a DMA trigger with the GPT ?
Is the CC2538 able to AND GPTA and GPTB ?
i don't know if it's possibe to do this with the CC2538 i was searching the user guide and i finded
nothing relevant.
thanks in advance,
Victor Roselló.