Hi,
I am using the TRF7960 target board to implement the ISO 14443a . I've allready done the ISO15693 and it is working fine but now I am having problems with the Anticollision command. First of all is that in sloa136.pdf is given the folowing example:
size is the number of bytes to be transmitted. In this case, size = 1.
buf[0] = 0x8f; /* Reset FIFO command */
buf[1] = 0x90; /* send with CRC */
buf[2] = 0x3d; /* write continuous from register 1D */
buf[3] = (char) (size >> 8); /* Data for register 1D */
buf[4] = (char) (size << 4); /* Data for register 1E */
buf[5] = 0x26; /* ISO14443A REQA command byte*/
In that case buf[3] should be 0x00 and buf[4] should be 0x10. I send this and I am not getting any interrupt. In the example source code in sloc251.zip, in the iso14443a.c file buf[3] and buf[4] are 0x00 and 0x0F in that order. When I send the package like that I get the END OF TX interrupt. So I am a little confused how it should be. And the second problem is that I don't allways get the END OF RX interrupt. I configure the "Chip Status Control (00h)" and the "ISO Control (01h)" as said in the documentation. When I get the END OF RX interrupt the "IRQ status register" is either 0x02 or 0x42. What value should I get, I am using only one tag in the field? Thank you in advance.
Regards, Todor.
The REQA command (0x26) and the WUPA command (0x52) for the ISO14443A tags are 7bits long rather than 1byte, so you have to set correctly the TX length on the registers 0x1D and 0x1E.
Example for 7bits command:
buf[3]=0x00;
buf[4]=0x0F; // zero bytes and 7bits with incomplete bytes bit set to 1.
I hope it will help you.
Bye!
Thank you, this explains my first issue, But I still have my other problem. I don't have any explanation why is that since the procedure is pretty much the same as in ISO15693 and it is working fine there.
Set the ISO_Control register to 0x88 to disable the RX CRC and set the ISO14443A standard at 106k. also set the chip_Status_Control register to 0x21.
after the end of TX interrupt, you should get the end of RX interrupt (0x40).
Let me know if it works!
bye
No still not working, After the END OF TX IRQ (IRQ status - 0x80) I get IRQ with status - 0x02,0x42 or timeout.
Any other suggestions?
Check better your registers configuration. Here there is mine:
Chip_Status_Control: 0x21
ISO_Control: 0x88
ISO14443B_TX_Options: 0x00
ISO14443A_HighBitRate_Options: 0x00
TX_Timer_HByte: 0xC1
TX_Timer_LByte: 0xC1
TX_PulseLength_Control: 0x20
RX_NoResponseWaitTime: 0x0E
RX_WaitTime: 0x07
Modulator_and_SYSClock_Control: 0x21
RX_SpecialSettings_Register: 0x20
Regulator_and_I/OControl: 0x06
IRQStatus_Register: 0x00
CollisionPosition_and_InterruptMaskRegister: 0x3E
CollisionPosition: 0x00
RSSILevel_and_OscillatorStatus_Register: 0x55
FIFO_Status: 0x00
TXLength_Byte1: 0x00
TXLength_Byte2: 0x00
Another hint could be this:
I had problems with missing the second interrupt due my interrupt routine was too much slow and not optimized. Even if you get the second interrupt with a value like 0x02 or 0x42, check in any case the status of the FIFO and read it. You may find there the ATQA answer!
If it will be so, try to optimize your code.
What should be the ATQA answer. I tried reading the FIFO status register after receiving 0x02 or 0x42 as IRQ status but it is allways 0x00 and there are no bytes in the FIFO.
Here is a sample image from my communication. After adding 6 ms delay after the initialisation of the registers and sending the command I got only one interrupt with 0xC0 status. What may be the cause of that.(ch1 - MOSI, ch2 - SCLK,ch3 - IRQ source,ch4 - MISO), Without these 6 ms the communication looks like this:
There are 3 IRQs with statuses - 0x80,0x02 and 0x40 but even after the last status is 0x40 there is still no data in the FIFO.
I am sorry to write again, but I don't know what to do anymore.
May you post your whole registers configuration before and after sending the command REQA?
Thanks
Here is my configuration before sending the ATQA request:
00: 21
01: 88
02: 00
03: 00
04: C1
05: C1
06: 20
07: 0E
08: 07
09: 31
0A: 20
0B: 06
0C: 00
0D: 3E
0E: 00
0F: 40
After sending the ATQA rewuest:
01: 08
0E: 7F
0F: 7F
Why the iso control register (0x01) changes from 0x88 to 0x08? It should always be 0x88 because the ATQA answer is without CRC so you have to set RX without CRC.
Let me know,
I set it to 0x08 after the REQA command because I saw this in the sample code. In this case is meaningless because when I send the anticollision command I set it again to 0x88. I will remove it from my code.
I made another screenshots of the communication and here are the results:
First I send ReqA command, it looks like this:
I send the command without CRC ( I set ISO control register to 0x88)
buf[0] = 0x8F;
buf[1] = 0x90;
buf[2] = 0x3D;
buf[3] = 0x00;
buf[4] = 0x0F;
buf[5] = 0x26;
After this command I get only one IRQ (I wait for timeout) with status 0xC0.Anyway I read the FIFO and there it is the ATQA respond -{0x04,0x00}.
Then I send Anticollision command again without CRC.
buf[4] = 0x20;
buf[5] = 0x93;
buf[6] = 0x20;
I get two IRQs with statuses 0xC0 and 0x40. Since there is only one card in the field i get the entire UID - 0x94 0x04 0xC1 0xB1 and one byte BCC - 0xE0.
After that I set ISO control register to 0x08 and send the select command:
buf[1] = 0x91;
buf[4] = 0x70;
buf[6] = 0x70;
buf[7] - buf[10] - UID
buf[11] - BCC;
Then I get one IRQ with status 0x80 and thats all. Nothing is happening from now on. Can anyone please tell me what am I doing wrong?Why sometimes there are two IRQs and sometimes only one?