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CC3000 SPI Clock Polarity and Phase
According to the CC3000 Host Programming Guide, "The clock and phase settings for the SPI are CPHA 0 and CPOL 0, meaning that the data is sampled on the falling edge of the clock cycle." However, from what I've read about SPI clock and phase settings for CPHA and CPOL, like the below from Wikipedia as well as my MCU's data sheet, CPHA=0 and CPOL=0 mean data is sampled on the clock's rising edge.
Am I misunderstanding something?
if you look for the MSP430 UG (just look for the document (MSP430FR5xx Family), then go to section 19.3.6, you would see that configuring CPHA and CPOL to 0 means that the data is propogated on rising edge and sampled on falling edge.
Shlomi, I believe you are mistaken.
The MSP430 UG does not indicate anything about CPOL and CPHA. Instead it mentions UCCKPL and UCCKPH. Though these serve the same function as CPOL and CPHA do in other systems, they do not conform to the CPOL and CPHA standards. Both UCCKPL and CPOL do match in their value definition (0 means clock is low when idle). However, UCCKPH and CPHA are opposite in their value definitions. For CPHA=0, data is sampled on the rising edge. For UCCKPH=0, however, data is sampled on the falling edge. Perhaps that is why they didn't call it CPHA.
Searching the internet, I do not seem anywhere but TI's CC3000 Host Programming Guide that claims CPHA=0 means sample on the falling edge. I believe this is a mistake in the CC3000 Host Programming Guide, which reads, "The clock and phase settings for the SPI are CPHA 0 and CPOL 0, meaning that the data is sampled on the falling edge of the clock cycle."
Here are examples showing CPHA=0 means sample on the rising edge:
Thanks for the clarification Jim,
It may be a mistake in the CC3000 Host Programming Guide. It would be fixed in case it is a mistake.
You are correct actually. It is configured as CPOL=0, CPHA=1 in the drivers.
Who is responsible to fix the Host Programming Guide? Could you contact them and let them know of this mistake. It still shows CPOL=0, CPHA=0. Let's get it done and save the next one to come along some valuable time.
we are in the process of issuing a new release.
it will be part of this release.
it is still not fixed, btw. would have been handy to know, like a few days ago.
in fact, it would be handier yet if the entire picture (like the one from wikipedia) was shown, showing the initial clock value is low, and then sample occurs on the transition from high to low. stated that way, there's no guessing.
also confusing is the distinction between 16 bit and 8 bit interfaces (the doc states 16 bit, the sample driver is 8 bit, and so on).
It is modified now but still lack a picture to more clearly explain it.
I am using non TI micro. So tell me which SPI mode i need to set. mode 0 or mode1.?
muku, i'm using microchip pic32mx. look at the cited wikipedia pages for definition of CPOL=0, CPHA=1.
if it helps, here's how i do it:
SpiChnOpen(chn, SPI_OPEN_MSTEN|SPI_OPEN_MODE16|SPI_OPEN_ENHBUF, div);
Thanks for ur reply, But i am using alters cyclone iV device, there i can configure SPI by modes only. I believe if CPOL=0, CPHA=1 means mode 1 as per my knowledge.
So shall i configure SPI to mode1?
Also i am using digiview logic analyzer to Capture SPI signals. What type of clock capture mode i have to select for MOSI & MIS)
Available capture option for SPI are
Clock MOSI on : "Falling Edge" or "Rising Edge" . I have selected FALLING EDGE here
Clock MISO on: "Falling Edge" or "Rising Edge" . I have selected RAISING EDGE here
Please correct me if i am wrong and also confirm the mode.
the diagram on wikipedia makes it very clear.
The documention adjustment is unclear and grammatically incorrect. Grammatically, you have two sentences joined by a comma with no conjunction. For clarity, you should specify the value of CPOL. You assume the reader will equate it to the specified value of UCCKPL, but you just said they are different naming conventions, so if the reader is to conclude CPOL is the same as UCCKPL, then you should say so.
You wrote, "The more generic convention is CPOL and CPHA, however, in order to configure sampling on the falling edge of the clock cycle, CPHA is set to 1".
This should be rewritten as, "The more generic convention is CPOL and CPHA, however. In order to configure sampling on the falling edge of the clock cycle, CPOL must set to 0 and CPHA must be set to 1."
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