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Hi Chrissy,

Thanks. I did not mean to confuse the two issues (boot & CpuTimer0). My question on CpuTimer0 is a separate issue.

So what happens when I power cycle the Control Card? Will the bootloader bug get in the way?

Tim

Tim11828

I was checking my Cpu clock setup yesterday and saw something that was puzzling. In the ARM I have:

 

// Setup main clock tree for 75MHz - M3 and 150MHz - C28x

        SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL |

                         (SYSCTL_SPLLIMULT_M & 0x0F)|SYSCTL_XCLKDIV_4);

 

 

And in C28 I have setup CpuTimer0 to interrupt:

ConfigCpuTimer(&CpuTimer0, C28_FREQ, 50);

 

But when I timed the rising and falling edge, I see 100 usec instead of 50. Some other setting I forgot?

Tim

4784.main_c28.txt

 

Tim,

At first glance it looks right.  I will need to look closer and get back to you.

This concludes Concerto office hours.  If you have a new question, please start a new post.

Tim,  I'm still looking at your last question.

Tim,

if your program control is stuck there, it means that control subsytem found some error while booting and it is not ready to accept IPC commands.

Can you send us the value that you see in CTOMIPCBOOTSTS registers on M3, when it is stuck waiting for control subsytem ready?

Best Regards

Santosh

Hi Santosh,

I will send that value to you. I am not in the office right now. Give me about an hour.

Tim

ok...also please send me the 32 bit values you see at the below locations too, along with CTOMIPCBOOTSTS.

on Master subsytem - 0x68047C

on Control Subsytem - 0x2403FE

Best Regards
Santosh

Tim,

I was able to get a hold of the pre-release copy of the bootROM guide which spells out exactly what you need to do to get your application running standalone on the C28. I had forgotten that the GEL files perform a RAM initialization during debug, but this must be done manually by an application before using the RAMs.  I've attached functions which do this.

I've been talking with Santosh and we believe you have a part whose OTP may not be programmed which can potentially cause the bootROM to ITRAP. Check the memory locations he requested first and report back, and then try these RAM Init functions.

4087.ipc_raminit.c

1.1      Guidelines To Concerto Boot ROM Application Writers

This section provides guidelines to write master subsystem application in-order to kick-start a peripheral boot loader on C-Boot ROM or to let control subsystem to boot to flash.

1.1.1            Master Subsystem Application Procedure to start C-Boot ROM boot loaders

As explained in the above boot rom sections, M-Boot ROM brings control subsystem out of reset so that it can execute C-Boot ROM and M-Boot ROM will continue to execute its own application. Mean-while C-Boot ROM initializes the control subsystem as explained and puts C28x CPU in IDLE Low Power Mode. It is up to the Master subsystem application to decide on how it wants to let control subsystem boot and function. The flow diagrams and procedures listed below in this section explain the minimum things that should be done in order to successfully boot control subsystem.

Figure 0‑11   Master Subsystem Application Flow To Start C-Boot ROM Loaders

Note: Please refer to next section for more details on Control Subsystem RAM-INIT procedure. Master application can avoid doing this RAM-INIT if control subsystem application in flash takes care of this by itself or if the user application code is downloaded to M0 RAM first, which Zero-initializes all the control subsystem RAMs before using them.

1.1.2            Master Subsystem Application Procedure to Initialize Control Subsystem RAM using IPC

As explained in section 1.6.2 all the control subsystem RAM, except for M0 RAM must be Zero-Initialized before they are used by Control subsystem applications, this is to avoid un-wanted RAM ECC errors because of un-initialized RAM locations.

MOTC IPC Commands should be used by master subsystem application to set bits in control subsystem registers to Zero-Initialize all control subsystem memories. The below code shows the procedure in detail.

Below are some defines that the code uses for ease of implementation, these registers are explicitly defined and described in Internal memories chapter of this document.  The below functions use IPCLITE driver library software to send IPC commands to C-Boot ROM. The IPCLITE driver library is released as part of header files release in F28M35x Concerto release.

Hi Santosh, Trey,

They are:

CTOMIPCBOOTSTS: 0x0

Master subsytem - 0x68047C (32 bits): 0x00000001

Control Subsytem - 0x2403FE: ---

Also in the screen shots attached.

Trey, I'm going to try the RAM Init functions next.

Tim

Hi Trey,

I called those 2 functions, and now it''s stuck at:

//wait until C-BootROM acks

        while(HWREG(MTOCIPC_BASE + IPC_O_MTOCIPCFLG) & IPC_FLAG1);

Thanks,

Tim

Hi Tim

thanks for the info. 

CTOMIPCBOOTSTS =0x0 - doesn't look good. something is wrong, so your RAM INIT code from M3 application will not run yet. We will find out what is wrong here.

for "Control Subsytem - 0x2403FE" location can you add *(0x2403FE) in your watch window and give me contents. It doesn't show up in your memory window.

Also can you give the contents of 0x20004000 location on master subsytem. 

along with above, can you also give below information, when the error happens.

1. disconnect everything in CCS  and connect back to master subsystem and control subsytem targets. Now both the cores are in DEBUG HALT. Can you give me the PC location for control subsystem or copy paste the dis-assembly window contents here.

2. Did you try running stand-alone? I assume master subsystem is booting properly to M-Flash. it is only your control subsystem that is not booting properly. How do you know your application is booting properly when testing in stand-alone. Do you toggle some IOs from both Master application and control subsystem applications in flash?

Best Regards
Santosh 

Hi Lori,

Once I got the C28 to boot out of Flash, CpuTimer0 worked as configured. I don't know what the relationship is, but the two seems to be related! I am still testing to verify that booting out of Flash works correctly, but thank you for your help!

Tim

Hi Trey, Santosh,

After repeated tries, the boot to Flash appears to be working. Initializing the RAM from M3 appears to fix the problem. I am going to run this some more to make sure there aren't anything else I overlooked.

Santosh, do you still want me to provide you with the data you asked for? I can send those over if you would still like to have them, it's not a problem. I could not get anything out of *(0x2403FE). I never had an issue with the Master subsystem. I was using the LEDs to verify that both sides were running correctly.

Also, my memory address input drop down box is very small. Is there a way to fix that? I saw screen shots some where else, and it's not like that. 

Thank you guys for the great support!!

Tim

Hi Tim

nice...you don;t have to provide that information. I wanted to make sure you have correct revision of data contents in TI memory space. It seems like you have because you got it to working.

Let us know if you have anymore questions.

Best Regards

Santosh

At this point I believe all the questions have been answered, so I am going to close the office hour thread.  If you have further questions about Concerto please start a new thread.

Thank you!

Lori