While I was debugging a project that uses the TMS320F28035, I noticed that issuing a "CPU reset" from debug mode seemed to change the timing of my code. Normally the values in the PLL registers are PLLSTS = 0x101 and PLLCR = 0x0C which is expected since I am running the TMS at 60MHz. After doing a "CPU reset" from CCS5, I noticed that the PLLSTS register changes such that PLLSTS = 0x181 and PLLCR = 0x0C. By reading the register descriptions in System Control and Interrupts datasheet for the chip, we see that the register values after the reset leaves the PLL multiplier at 12 and changes the PLL division to 1 - which seems to indicate that I am running the system clock at 120MHz (beyond the chip specifications). According to the datasheet, the DIVSEL bits of the PLLSTS register cannot be set to divide by 1 unless the PLL is off or bypassed, but all indications seem to suggest that the chip is indeed running at 120MHz. Functionality is identical but performs twice as fast as usual. Furthermore, I tested this theory by measuring the system clock on the XCLKOUT gpio using an oscilloscope and in fact measured 120MHz. After verifying this I discovered that I could configure the PLL registers to the "CPU reset" state in the code and have the chip run at 120MHz. So far I have not found any information regarding this behavior. Is it possible to use the TMS320F28035 at 120MHz but simply not recommended?
No, the TMS320F28035 is only characterized to run at a maximum of 60MHz as indicated in the datasheet.
Brandon
I know the datasheet says that 60MHz is the max, but what happens if the PLL is configured as I've described (i.e. x12 and /1)? Also, how am I getting 120MHz as my SYSCLK out?
Benjamin Paik I know the datasheet says that 60MHz is the max, but what happens if the PLL is configured as I've described (i.e. x12 and /1)?
I know the datasheet says that 60MHz is the max, but what happens if the PLL is configured as I've described (i.e. x12 and /1)?
Your observations seem to indicate that this configuration will produce a clock frequency of 120MHz which is out of specification of the device. Proper operation of the device is not guarenteed beyond the stated maximum in the datasheet.
Benjamin Paik Also, how am I getting 120MHz as my SYSCLK out?
Also, how am I getting 120MHz as my SYSCLK out?
Within the CCSv5 environment, do you have a GEL file included in the target configuration? If so, perhaps this is getting run upon a CPU reset which is incorrectly configuring the PLL to this setting. If so, that should be corrected.
I could not find any GEL file in my project directory or anywhere on my C drive. Does CCSv5.2.11 use anything by default?
I'm not familiar with CCSv5.2.11. My version is CCSv5.1.0.09000 which is currently of the v5.1 versions that support all ISAs. The v5.2 line is currently limited to MSP430 and C6000.
The GEL file would be referenced as part of the Target Configuration file (ie. the .ccxml) file used by CCS to describe your target hardware.
When I created a new target configuration file for the TMS320F28035, it automatically added ..\..\emulation\gel\f28035.gel to the TMS320F28035_0->C28xx device in the Advanced settings tab of the Target Configuration file.