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I've been using my F28069 control stick and using the EPWM1 to drive the ADC sampling rate.  I was assuming the chip was running at 80 MHz, but my sampling rate showed otherwise.  I see that a 6 MHz resonator is being used as the input to the pll (verified with scope).  I see the software comments and defines (in ...examples.h)
indicate a 10 MHz input was expected - 10 MHz * 16 (PLLCR) / 2 (div) = 80 MHz.  So I'm guessing this explains part of the sampling rate difference.

I wanted to run the DSC at a rate at least closer to 80 MHz, so I changed the PLLCR value to 12 and the divisor to 1 (defined in the ...examples.h file).  I thought this should give me a rate of 6 MHz * 12 / 1 = 72 MHz.  However, when when I set the TBPRD to 5000 (CMPR to 1/2 of that, set to count up mode I believe), I was expecting a sample rate of 72 MHz / 5000 = 14.4 kHz, but instead I get a sample rate of 12 KHz. 

So, I don't know if the actual system clock rate is 60 MHz instead of 72 MHz (as I programmed), or if there is a division of the system clock to the EPWM clock that I don't know about. 

I've checked the forums as best I can, but I don't see anyone saying they think their DSC runs slower than 80 MHz.  Am I missing something?

By the way, I thought perhaps the info on PLLCR and divisor might be incorrect, so I changed both to give me the 14.4 kHz sample rate I expected, but the chip began to flake out (ITRAP, etc) so it makes me think I'm running the chip beyond 80 MHz.

Do you have any insight as to why the sample rate is slower than expected?  If necessary, I can send code.

Thanks,

Brad