TI E2E Community
C2000 32-bit Microcontrollers Forum
F28m35H52 M3 GPIO monitoring
I am working with Concerto evaluation kit running the RT_sineFIRFFT example. I am trying to monitor a GPIO that is controlled by the C28 core from the M3 side.
GpioG1CtrlRegs.GPCDIR.bit.GPIO70 = 1;
GpioG1DataRegs.GPCDAT.bit.GPIO70 = 1;
in timer interrpt
GpioG1DataRegs.GPCDAT.bit.GPIO70 = ~GpioG1DataRegs.GPCDAT.bit.GPIO70 & 0x0001; is working fine toggles led
On the M3 side i added HWREG(GPIO_PORTC_BASE + GPIO_O_DEN) |= GPIO_PIN_6; this sets the GPIODEN register to 0xd0 which I thought would enable me to read the pin using
ret = GPIOPinRead (GPIO_PORTC_BASE, GPIO_PIN_6);
I can read this GPIO when i control it on the M3 side using something like
GPIOPinConfigureCoreSelect(GPIO_PORTC_BASE, ( GPIO_PIN_6 ), GPIO_PIN_M_CORE_SELECT); GPIOPinTypeGPIOOutput (GPIO_PORTC_BASE,GPIO_PIN_6); GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_6, ~0);
could you please offer me some advice as to the setting for gpio registers for monitoring C28 controlled outputs/inputs from the M3 \
This is a bug which will be included in the next revision of the F28M35x errata. Currently, you cannot read the value of an IO from the core which does not have ownership of the IO. This will be fixed in Rev A of the device.
do you have a launch date for that revision?
Not sure we have an exact date on it yet, but I believe it will be sometime 1H13.
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