A customer frequently met BRKDT interrupt on F28027 when he used SCI adress mode with 19200bps. As SCI user guide description, a break detect condition occurs (the SCIRXD is low for ten bit periods following a missing stop bit). So have some questions as below on break condition.
1. Does the ten bit periods is low include start bit? The ten low bit perios will be appeared always if address bit is 0 and data is 0x00.
2. Does break dectect if SCITXD didn't miss stop bit,but data line remained continuously low more than ten bit periods?
3. Has any other thing cause SCI break interrupt? How to find the root reason and solve it?
Thanks in advance!
1. Yes, start bit is included in the ten low bit count for BRKDT.
2. The condition for BRKDT is that after a missing stop bit, there should be ten continuous low bits. So, for your question, after a stop bit, if RX line is low continuously for 10 bits it causes a frame error as 10th bit is stop bit and is missing. After this first missing stop bit, if ten more bit durations are low on RX, then a BRKDT occurs.
3. No, only ten continuous low bits after a missing stop bit can cause BRKDT.
I think there is still an unanswered question - How to find a root cause of BRKDT condition and solve it? What can be the condition for missing the stop bit.
I also work with F28027. Data should be received as 4 bytes every 10ms at 9600 baud rate. But, the BRKDT condition is detected too often to have a reliable communication. When BRKDT is detected, the SWRESET flag is toggled (as recommended by the documentation - sprugh1c.pdf), and the communication recovers - that's ok. But BRKDT happens too often. I would like to figure out why. Any help/advice would be highly appreciated.
Thanks a lot,Slavica
Resolved: The break on the line was due to noise. It required a hardware change to solve the problem. BRKDT condition does not happen anymore.
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