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  • TI Thinks Resolved

CCS/LAUNCHXL-F28379D: Trip_zone configuration

Part Number: LAUNCHXL-F28379D

Tool/software: Code Composer Studio

Hello

configured the TZ in my program like this when i run it with out SC the TZ GPIO24 or 59

it is tripping (no PWM wave), that means it is not entering to ISR 


#include "F28x_Project.h"
#include "math.h"
#include <stdio.h>
#include <stdlib.h>
#define PWM_Prd 10000;
#define Phi1 1500; // (625)45 DEG PHASE
#define Phi2 1500; // (625)45 DEG PHASE
#define PI 3.14159265358979323846

//Uint32 EPwm1TZIntCount;
//Uint32 EPwm2TZIntCount;
//void InitTzGpio(void);
void InitEPwm1_2Example(void);
void LED_init(); //LED on control card
//void InitEPwm2Example(void);//void InitEPwm3Example(void);//void InitEPwm4Example(void);//void InitEPwm5Example(void);//void InitEPwm6Example(void);
//void InitEPwmGpio_TZ(void);
__interrupt void epwm1_isr(void);
unsigned int i=0,m=0,k=0;
unsigned int a=0;
unsigned int b[101]={0};
void main(void)
{
InitSysCtrl();
for(m=0;m<100;m++)
{
a=sin(PI*0.02*m);
b[m]= 5000*a + 5000; //50% HALF SINE WAVE cycle.
}
b[100]=0;
InitGpio();
EALLOW;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
InitEPwm6Gpio();
// InitTzGpio(); //TZ1 = GPIO12, TZ2 = GPIO13
// InitEPwmGpio_TZ();
//GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1;
EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.EPWM1_INT = &epwm1_isr;
InitEPwm1_2Example();
//InitEPwm2Example();//InitEPwm3Example();//InitEPwm4Example(); //InitEPwm5Example(); //InitEPwm6Example();
EDIS;
IER |= M_INT3;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
for(;;)
{
asm (" NOP");
}
}
__interrupt void epwm1_isr(void)
{
GpioDataRegs.GPBDAT.bit.GPIO52 = 1;
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // GPIO26 = GPIO26 //GREEN_1
if (EPwm1Regs.TZFLG.bit.OST == 0 && EPwm2Regs.TZFLG.bit.OST == 0)
{//IF#1 No fault,perform the ISR
a=sin(PI*0.02*i);
if (a>=0)
{//if#2
EPwm1Regs.CMPA.bit.CMPA =b[i]; //EPwm1Regs.CMPB.bit.CMPB =b[i];
EPwm2Regs.CMPA.bit.CMPA =b[i]; // EPwm2Regs.CMPB.bit.CMPB =b[i];
EPwm3Regs.CMPA.bit.CMPA =b[i]; // EPwm3Regs.CMPB.bit.CMPB =b[i];
EPwm4Regs.CMPA.bit.CMPA =b[i]; // EPwm4Regs.CMPB.bit.CMPB =b[i];
EPwm5Regs.CMPA.bit.CMPA =b[i];// EPwm5Regs.CMPB.bit.CMPB =b[i];
EPwm6Regs.CMPA.bit.CMPA =b[i];// EPwm6Regs.CMPB.bit.CMPB =b[i];
}
else
{//else for if#2
EPwm1Regs.CMPA.bit.CMPA =b[i];// EPwm1Regs.CMPB.bit.CMPB =b[i];
EPwm2Regs.CMPA.bit.CMPA =b[i];// EPwm2Regs.CMPB.bit.CMPB =b[i];
EPwm3Regs.CMPA.bit.CMPA =b[i];// EPwm3Regs.CMPB.bit.CMPB =b[i];
EPwm4Regs.CMPA.bit.CMPA =b[i];// EPwm4Regs.CMPB.bit.CMPB =b[i];
EPwm5Regs.CMPA.bit.CMPA =b[i];// EPwm5Regs.CMPB.bit.CMPB =b[i];
EPwm6Regs.CMPA.bit.CMPA =b[i];// EPwm6Regs.CMPB.bit.CMPB =b[i];
}//end of else for if#2
i++;
if (i==101)
{ //if#3
i=0; }//end of if#3

EALLOW;
//EPwm1Regs.TZCLR.bit.OST = 1;
//EPwm1Regs.TZCLR.bit.INT = 1;
EDIS;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
GpioDataRegs.GPBDAT.bit.GPIO52 = 0;
}//end of if#1 TZ1 for Pwm rectifier fault
else //one-shot fault
{//else for if#1
GpioDataRegs.GPBDAT.bit.GPIO52 = 0;
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // GPIO25 = GPIO25 //RED
}//end of else for if#1

}//end of ISR
void InitEPwm1_2Example()
{

GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // GPIO27 = GPIO27 //GREEN_2 this led is glowing 

// // Setup counter mode //
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
// Clock Settings
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// Set compare A value
EPwm1Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on event A, up
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event B, down
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event A, up
EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM1B on event B, down
//PWM settings
EPwm1Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0;
// // Setup counter mode //
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Set PWM1A on event A, up
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM1A on event B, down
EPwm2Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B on event A, up
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm2Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm2Regs.TBCTR = 0;
// // Setup counter mode //
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm3Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on event A, up
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event B, down
EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Set PWM1B on event A, up
EPwm3Regs.AQCTLB.bit.CBU = AQ_SET; // Clear PWM1B on event B, down
EPwm3Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm3Regs.TBPHS.bit.TBPHS = 10000 - Phi1; // Phase is 0
EPwm3Regs.TBCTR = 0;
// // Setup counter mode //
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm4Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Set PWM1A on event A, up
EPwm4Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM1A on event B, down
EPwm4Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B on event A, up
EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm4Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm4Regs.TBPHS.bit.TBPHS = 10000-Phi1; // Phase is 0
EPwm4Regs.TBCTR = 0;
// // Setup counter mode //
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm5Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on event A, up
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event B, down
EPwm5Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event A, up
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm5Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm5Regs.TBPHS.bit.TBPHS = 10000 - Phi2; // Phase is 0
EPwm5Regs.TBCTR = 0;

// // Setup counter mode //
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Set PWM1A on event A, up
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM1A on event B, down
EPwm6Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B on event A, up
EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm6Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm6Regs.TBPHS.bit.TBPHS = 10000 - Phi2; // Phase is 0
EPwm6Regs.TBCTR = 0;

//***Trip ZONE***//
EALLOW;
//GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // GPIO25 = GPIO25 //RED
//Set triped sources
EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE; //TZ1 as one shot
// EPwm2Regs.TZSEL.bit.OSHT1 = TZ_ENABLE; //TZ1 as one shot
// EPwm3Regs.TZSEL.bit.OSHT1 = TZ_ENABLE; //TZ1 as one shot
// EPwm1Regs.TZSEL.bit.CBC2 = TZ_ENABLE; //TZ2 as Cycle by cycle
// EPwm2Regs.TZSEL.bit.CBC2 = TZ_ENABLE; //TZ2 as Cycle by cycle
// EPwm3Regs.TZSEL.bit.CBC2 = TZ_ENABLE; //TZ2 as Cycle by cycle
//Set trip action
// EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; //PWM1A goes low when triped
// EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //PWM1B goes low when triped
// EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; //PWM2A goes low when triped
// EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //PWM2B goes low when triped
// EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; //PWM3A goes low when triped
// EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //PWM3B goes low when triped
///
// EPwm5Regs.TZCTL.bit.TZA = TZ_FORCE_LO; //PWM5A goes low when triped
// EPwm5Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //PWM5B goes low when triped
// EPwm6Regs.TZCTL.bit.TZA = TZ_FORCE_LO; //PWM6A goes low when triped
// EPwm6Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //PWM6B goes low when triped
// EPwm1Regs.TZEINT.bit.OST = 1;
EDIS;
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // GPIO25 = GPIO25 //RED
// Enable INT Settings
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd evenT
// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // GPIO25 = GPIO25 //RED
}

void LED_init()
{
EALLOW;
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // GPIO25 = GPIO25 //RED
// GPIO-39 - PIN FUNCTION = LED10 on controlCARD
//GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 0; // 0=GPIO, 1=CANTX-A, 2=Resv, 3=Resv
//GpioCtrlRegs.GPBDIR.bit.GPIO39 = 1; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO39 = 1; // uncomment if --> Set Low initially
//GpioDataRegs.GPBSET.bit.GPIO39 = 1; // uncomment if --> Set High initially

// GPIO-34 - PIN FUNCTION = LED9 on controlCARD
//GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // 0=GPIO, 1=COMP2OUT, 2=EPWMSYNCI, 3=ADCSOCA
//GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // 1=OUTput, 0=INput
// GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; // uncomment if --> Set Low initially
//GpioDataRegs.GPBSET.bit.GPIO34 = 1; // uncomment if --> Set High initially

// GPIO-52 - PIN FUNCTION = LED GREEN
// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 0; //
// GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1; // 1=OUTput, 0=INput
// GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPBSET.bit.GPIO52 = 1; // uncomment if --> Set High initially


// GPIO-53 - PIN FUNCTION = LED GREEN
// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 0; //
// GpioCtrlRegs.GPBDIR.bit.GPIO53 = 1; // 1=OUTput, 0=INput
// GpioDataRegs.GPBCLEAR.bit.GPIO53 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPBSET.bit.GPIO53 = 1; // uncomment if --> Set High initially
// GPIO-56 - PIN FUNCTION = LED RED
// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0; //
// GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1; // 1=OUTput, 0=INput
// GpioDataRegs.GPBCLEAR.bit.GPIO56 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPBSET.bit.GPIO56 = 1; // uncomment if --> Set High initially
EDIS;
}

Nageswara Rao kudithi

  • Hi Nageswara,

    I don't understand the question. What is the problem you are seeing and what is the desired behavior? Can you post a waveform?

    Regards,
    Kris
  • In reply to Kris Parrent:

    Hi Kudithi,

    Since we didn't hear a response for several weeks, we are going to assume that you were able to resolve the issue. If this isn't the case, please reject the resolution or just reply to the thread with the current status of your issue.

    Did a reply answer your question? If yes, please click the "Resolved" button located at the bottom of that post.
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