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CCS/F28M36P63C2: Problems when using sharing blocs memory

Prodigy 130 points

Replies: 6

Views: 133

Part Number: F28M36P63C2

Tool/software: Code Composer Studio

hello everyone;

I'm trying to copy a constant from an input port to a specific address in the shared memory, the program is running on the M3 core. unfortunately, It didn't work.

for some addresses, Code Composer Studio stop running and exit automatically (for example 20009FF0 and 20008000 in S0 RAM).

for some other addresses, the program copies the value but the M3 core stop running (for example 2000AAAA in S1 RAM). 

for other addresses, the program still running but enable to copy the value.

  How can I found the best address to do that?

thanks in advance;

best Regards;

Yahya;

  • Yahya,

    It sounds like you may be running out of memory in your application. Can you try expanding or combining memory blocks as explained here: processors.wiki.ti.com/.../C28x_Compiler_-_Understanding_Linking and seeing if that helps address the conditions in which it stops running.

    I would also recommend you start out with the linker command file templates provided in controlSUITE

    Regards,
    Ozino

  • In reply to Ozino Odharo:

    Hi, Ozino;

    thank you very much for your helpful reply, yes for my application I'm using the following linker command file templates provided in controlSUIT
    C:\MATLAB\SupportPackages\R2016a\toolbox\target\supportpackages\tic2000_concerto\src\F28M36P63C2_m3.cmd but when editing it, it doesn't contain the Sx RAM blocs in memory map.


    --retain=g_pfnVectors

    #ifdef BOOT_FROM_FLASH=1 */
    --retain=dcsm_z1_secvalues.obj(.z1secvalues,.z1_csm_rsvd)
    --retain=dcsm_z2_secvalues.obj(.z2secvalues,.z2_csm_rsvd)

    /* System memory map */

    MEMORY
    {
    /* Flash Block 0, Sector 0 Z1 CSM */
    CSM_ECSL_Z1 : origin = 0x00200000, length = 0x0024
    CSM_RSVD_Z1 : origin = 0x00200024, length = 0x000C

    /* Flash Block 0, Sector 0 */
    RESETISR (RX) : origin = 0x00200030, length = 0x0008 /* Reset ISR is mapped to boot to Flash location */
    INTVECS (RX) : origin = 0x00201000, length = 0x0258
    FLASHLOAD (RX) : origin = 0x00201258, length = 0x6DA8 /* For storing code in Flash to copy to RAM at runtime */

    /* Flash Block 0, Sector 1 to Flash Block 0, Sector 13 */
    FLASH (RX) : origin = 0x00208000, length = 0xF7E00 /* Sector 1 thru Sector 13 (minus Z2 CSM) */

    /* Flash Block 0, Sector 13 Z2 CSM*/
    CSM_RSVD_Z2 : origin = 0x002FFE00, length = 0x01DC
    CSM_ECSL_Z2 : origin = 0x002FFFDC, length = 0x0024

    /* RAM */
    C0 (RWX) : origin = 0x20000000, length = 0x2000
    C1 (RWX) : origin = 0x20002000, length = 0x2000
    BOOT_RSVD (RX) : origin = 0x20004000, length = 0x0FF8
    C2 (RWX) : origin = 0x200051B0, length = 0x0E50
    C3 (RWX) : origin = 0x20006000, length = 0x2000

    C4 (RWX) : origin = 0x20018000, length = 0x2000
    C5 (RWX) : origin = 0x2001A000, length = 0x2000
    C6 (RWX) : origin = 0x2001C000, length = 0x2000
    C7 (RWX) : origin = 0x2001E000, length = 0x2000
    C8 (RWX) : origin = 0x20020000, length = 0x2000
    C9 (RWX) : origin = 0x20022000, length = 0x2000
    C10 (RWX) : origin = 0x20024000, length = 0x2000
    C11 (RWX) : origin = 0x20026000, length = 0x2000
    C12 (RWX) : origin = 0x20028000, length = 0x2000
    C13 (RWX) : origin = 0x2002A000, length = 0x2000
    C14 (RWX) : origin = 0x2002C000, length = 0x2000
    C15 (RWX) : origin = 0x2002E000, length = 0x2000

    CTOMRAM (RX) : origin = 0x2007F000, length = 0x0800
    MTOCRAM (RWX) : origin = 0x2007F800, length = 0x0800
    }

    /* Section allocation in memory */

    SECTIONS
    {
    .intvecs: > INTVECS
    .resetisr: > RESETISR
    .text : > FLASH
    .const : > FLASH
    .cinit : > FLASH
    .pinit : > FLASH

    .vtable : > C0 | C1 | C2 | C3 | C4
    .data : > C2 | C3 | C4
    .bss : >> C2 | C3 | C4
    .sysmem : > C2 | C3
    .stack : > C2 | C3 | C4

    .z1secvalues : > CSM_ECSL_Z1
    .z1_csm_rsvd : > CSM_RSVD_Z1
    .z2secvalues : > CSM_ECSL_Z2
    .z2_csm_rsvd : > CSM_RSVD_Z2


    ramfuncs : LOAD = FLASHLOAD,
    RUN = C0,
    LOAD_START(RamfuncsLoadStart),
    LOAD_SIZE(RamfuncsLoadSize),
    LOAD_END(RamfuncsLoadEnd),
    RUN_START(RamfuncsRunStart),
    RUN_SIZE(RamfuncsRunSize),
    RUN_END(RamfuncsRunEnd),
    PAGE = 0

    GROUP : > MTOCRAM
    {
    PUTBUFFER
    PUTWRITEIDX
    GETREADIDX
    }

    GROUP : > CTOMRAM
    {
    GETBUFFER : TYPE = DSECT
    GETWRITEIDX : TYPE = DSECT
    PUTREADIDX : TYPE = DSECT
    }
    }

    #else
    MEMORY
    {
    C0 (RWX) : origin = 0x20000000, length = 0x2000
    C1 (RWX) : origin = 0x20002000, length = 0x2000
    BOOT_RSVD (RX) : origin = 0x20004000, length = 0x0FF8
    RESETISR (RWX) : origin = 0x20004FF8, length = 0x0008
    INTVECS (RWX) : origin = 0x20005000, length = 0x0258
    C2 (RWX) : origin = 0x20005258, length = 0x0DA8
    C3 (RWX) : origin = 0x20006000, length = 0x2000

    C4 (RWX) : origin = 0x20018000, length = 0x2000
    C5 (RWX) : origin = 0x2001A000, length = 0x2000
    C6 (RWX) : origin = 0x2001C000, length = 0x2000
    C7 (RWX) : origin = 0x2001E000, length = 0x2000
    C8 (RWX) : origin = 0x20020000, length = 0x2000
    C9 (RWX) : origin = 0x20022000, length = 0x2000
    C10 (RWX) : origin = 0x20024000, length = 0x2000
    C11 (RWX) : origin = 0x20026000, length = 0x2000
    C12 (RWX) : origin = 0x20028000, length = 0x2000
    C13 (RWX) : origin = 0x2002A000, length = 0x2000
    C14 (RWX) : origin = 0x2002C000, length = 0x2000
    C15 (RWX) : origin = 0x2002E000, length = 0x2000

    CTOMRAM (RX) : origin = 0x2007F000, length = 0x0800
    MTOCRAM (RWX) : origin = 0x2007F800, length = 0x0800
    }

    /* Section allocation in memory */

    SECTIONS
    {
    .intvecs: > INTVECS
    .resetisr: > RESETISR
    .text : >> C0 | C1 | C2 | C3
    .const : >> C0 | C1 | C2 | C3 | C4
    .cinit : > C0 | C1 | C2 | C3 | C4
    .pinit : >> C0 | C1 | C2 | C3

    .vtable : >> C0 | C1 | C2 | C3 | C4
    .data : >> C2 | C3
    .bss : >> C2 | C3 | C4
    .sysmem : > C2 | C3 | C4
    .stack : > C0 | C1 | C2 | C3


    GROUP : > MTOCRAM
    {
    PUTBUFFER
    PUTWRITEIDX
    GETREADIDX
    }

    GROUP : > CTOMRAM
    {
    GETBUFFER : TYPE = DSECT
    GETWRITEIDX : TYPE = DSECT
    PUTREADIDX : TYPE = DSECT
    }
    }
    #endif

    //__STACK_TOP = __stack + 256;

    can I include Sx RAM blocs in this linker command file?

    Thanks in advance;

    Best Regards;
    Yahya;
  • In reply to Ozino Odharo:

    Hi Ozino;

    when the program copies the value and the M3 core stop running the following message occurs in CCS's console:

    Cortex_M3_0: SemiHosting : File IO Error : fopen() : ÿÿ : No such file or directory

    Cortex_M3_0: Trouble Reading Register SPSR_SVC: (Error -1064 @ 0x400271) Attempted to access an unknown or invalid register. Confirm the register is valid and accessible, and retry the operation. (Emulation package 5.1.507.0)

    Cortex_M3_0: SemiHosting : Read Failure : Register: SPSR_SVC

    Best Regards;

    Yahya;

  • In reply to kissi yahya:

    Yahya,

    With regards to the Sx RAM blocks, have you correctly configured memory subsystem to use Sx-0 RAM as Shared memory?

    If not, please checkout the TRM chapters on Sx RAM and configuraing the mem configuration register(pg 84, 191, 487) in spruhe8d.

    Here is a forum post below with a similar issue:
    e2e.ti.com/.../267543

    Regards,
    Ozino

  • In reply to Ozino Odharo:

    Hi Ozino;

    thank you very much for your help; you're right, I must give the ownership of the shared memory blocks to the C28 processor, by setting the appropriate bits in the 

     Sx SHRAM Master Select Register (MSxMSEL) (spruhe8d page 480); Now it works fine.

    Best Regards;

     Yahya;

  • In reply to kissi yahya:

    Yahya,

    Glad to hear that you were able to get this isssue resolved. Thanks for sharing your findings.

    Regards,
    Ozino

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