28335: How exactly does the ECap Compare logic work?

Hi,

I'm using an ECap Unit in APWM mode and I'm looking for information on how exactly the "PWM Compare Logic" block of an 28x ECap Unit works. I'm referring to the block in the right upper corner of Fig. 3 of spu807b.pdf.

Particularly, I'd like to know, if the level of the output pin depends on the values of TSCTR and ACMP  (i.e, pin = 0 for TSCTR < ACMP and pin = 1 for TSCTR >= ACMP or similar). Or is the pin set when TSCTR = ACMP and reset when TSCTR = APRD (or 0)?

Regards, Johannes

  • Johannes L.
    I'm using an ECap Unit in APWM mode and I'm looking for information on how exactly the "PWM Compare Logic" block of an 28x ECap Unit works. I'm referring to the block in the right upper corner of Fig. 3 of spu807b.pdf.

    Johannes,

    Figure 3 is for the eCAP when it is configured as a capture module.  Figure 2 shows the functionality when the eCAP is configured in APWM mode.  In this mode CAP1/2 become the compare value - this value is compared against the counter and the specified action is taken when they match (ie pull the output pin hi/low). 

    Does it make more sense now?

    -Lori

  • In reply to Lori Heustess:

    Also if you have a 280x you can try the APWM example in http://www.ti.com/tool/sprc191

    Cheers

    Lori

  • In reply to Lori Heustess:

    Hi Lori,

    thank you for your response.

    Lori Heustess

    Figure 3 is for the eCAP when it is configured as a capture module.  Figure 2 shows the functionality when the eCAP is configured in APWM mode.  In this mode CAP1/2 become the compare value - this value is compared against the counter and the specified action is taken when they match (ie pull the output pin hi/low). 

    Does it make more sense now?

    Fig. 2 doesn't explain much more detail of the PWM Compare logic than Fig. 3. But from your explanation I figure that Compare Match and Period Events affect the output rather than the conditions TSCTR < CMPR and TSCTR >= CMPR.

    The background of my question was that I couldn't conclude from the docs the behaviour of the output for the case when TSCTR jumps from a value <CMPR to a value >CMPR due to SyncIn and CTRPHS>CMPR. If the Compare Match (i.e. TSCTR == CMPR) affects the output I would expect the output to remain at the level it had before SyncIn even though TSCTR > CMPR until the next event (match or period occurs).

    Regards, Johannes

  • In reply to Johannes L.:

    Johannes L.
    Fig. 2 doesn't explain much more detail of the PWM Compare logic than Fig. 3. But from your explanation I figure that Compare Match and Period Events affect the output rather than the conditions TSCTR < CMPR and TSCTR >= CMPR

    Yes exactly.  The code and diagrams in section 8 of www.ti.com/lit/sprufg4 may help to clarify.

    Johannes L.

    The background of my question was that I couldn't conclude from the docs the behaviour of the output for the case when TSCTR jumps from a value <CMPR to a value >CMPR due to SyncIn and CTRPHS>CMPR. If the Compare Match (i.e. TSCTR == CMPR) affects the output I would expect the output to remain at the level it had before SyncIn even though TSCTR > CMPR until the next event (match or period occurs).

    If the counter jumps over the compare value then the match will not occur - in this case the expectation is the output would remain until the next event (period, zero, compare match..) changes it.   I agree the documentation needs improvement in this area and will send the feedback to the team.

    Regards

    Lori

     

     

     

     

     

  • In reply to Lori Heustess:

    Johannes,

    I think the below diagram might help - it shows the compare "equal-to" clears a D-flop.  In the case you mention this care equal would be missed.

    -Lori