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C2000 32-bit Microcontrollers Forum
2812 timer interrupt urgent !
I was trying to write an assembly program to run an ISR during a timer period interrupt. I had configured all my timer control registers and peripheral clocks required for this. I had also populated the PIE vector table with ".sect directive". When an interrupt occurs, I can see the interrupt vector ID in the PIECTRL register but the service routine is not getting executed. I suspect it is not at all entering into the ISR. I had been trying this for so long. Kindly help me in this regard.
Are you sure you have all of the interrupts enabled? Keep in mind that both the global interrupt flag, the global IER register, and the PIE IER register must be setup for an interrupt to execute.
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Yes I had initially disabled all the interrupts. I made IER = 0x0000 and disabled PIECTRL. then initialized all sys control registers. initialized timers and then enabled PIEIER. I had followed the flowchart as given in the interrupts reference guide. I was just trying to increment the contents of auxilary register during a period interrupt. Coukd you please give me a sample assembly language program so that I'll get some idea?
While the F2812 isn't really supported within controlSUITE there is still some example software laying around. I'm not sure if this package will have exactly the assembly code you are looking for, it should have some C examples of how to setup the interrupts. Take a look at sprc097:
try defining the ISR function in assmebly as .sect ".Isr", when we write ISRs in C we have to use interrupt key word, I would assume you will have to do that for assembly routines as well.
Let us know if it works.
I had already seen the mixed source of many c languages to get an idea but unfortunately I couldnt make out anything. Could you please tell me the procedure that has to be followed to service an interrupt in an assembly language? I had initialized the PIE vector table with . sect and .long directives. Do we need to follow a sequence while writing these directives. If yes, how does the interrupt source identify that it has to go to a particular offset in the table?
I had defined the reset vector with .sect ".reset" vectors with .sect ".vectors" and Pie vectors with .sect ".pievect". And then using .long directive I had initialized all the interrupt. All the interrupts except the one I am using are made dummy. and then I wrote a MAIN loop. At the end of the main loop, I had USED B MAIN instruction
along with enabling all the interrupt enabled bits (at PIE level, at CPU level (IER) and the EINT) as Trey suggested, you will have to register the handler with PIE (look at examples Trey pointed out at) . As I said along with all above we define ISRs in C with an interrupt key word, so that the assembler can put the right instructions for stack save and return.
I would suggest to look at the generated assembly for a C-style declared/defines ISR and follow the same in your assembly interrupt routine defnition.
In the mixed assembly source, He was changing the stackpointer at every interrupt. I thought initializing a PIE vector table and defining an ISR would be an easier task than to manually handle the interrupts
This is how I had initialized the table. Kindly tell me what should be the instructions after this if I want to execute Timer1 Period Interrupt.
VECT: .sect "vectors" .long INIT .long ISR1 .long ISR2 .long ISR3 .long ISR4 .long ISR5 .long ISR6 .long ISR7 .long ISR8 .long ISR9 .long ISR10 .long ISR11 .long ISR12 .long ISR13 .long ISR14 .sect "pievt"PIEVT: .long ISR1_1 .long ISR1_2 .long ISR1_3 .long ISR1_4 .long ISR1_5 .long ISR1_6 .long ISR1_7 .long ISR1_8 .long ISR2_1 .long ISR2_2 .long ISR2_3 .long SINE .long ISR2_5 .long ISR2_6 .long ISR2_7 .long ISR2_8 .long ISR3_1 .long ISR3_2 .long ISR3_3 .long ISR3_4 .long ISR3_5 .long ISR3_6 .long ISR3_7 .long ISR3_8 .long ISR4_1 .long ISR4_2 .long ISR4_3 .long ISR4_4 .long ISR4_5 .long ISR4_6 .long ISR4_7 .long ISR4_8 .long ISR5_1 .long ISR5_2 .long ISR5_3 .long ISR5_4 .long ISR5_5 .long ISR5_6 .long ISR5_7 .long ISR5_8 .long ISR6_1 .long ISR6_2 .long ISR6_3 .long ISR6_4 .long ISR6_5 .long ISR6_6 .long ISR6_7 .long ISR6_8 .long ISR7_1 .long ISR7_2 .long ISR7_3 .long ISR7_4 .long ISR7_5 .long ISR7_6 .long ISR7_7 .long ISR7_8 .long ISR8_1 .long ISR8_2 .long ISR8_3 .long ISR8_4 .long ISR8_5 .long ISR8_6 .long ISR8_7 .long ISR8_8 .long ISR9_1 .long ISR9_2 .long ISR9_3 .long ISR9_4 .long ISR9_5 .long ISR9_6 .long ISR9_7 .long ISR9_8 .long ISR10_1 .long ISR10_2 .long ISR10_3 .long ISR10_4 .long ISR10_5 .long ISR10_6 .long ISR10_7 .long ISR10_8 .long ISR11_1 .long ISR11_2 .long ISR11_3 .long ISR11_4 .long ISR11_5 .long ISR11_6 .long ISR11_7 .long ISR11_8 .long ISR12_1 .long ISR12_2 .long ISR12_3 .long ISR12_4 .long ISR12_5 .long ISR12_6 .long ISR12_7 .long ISR12_8 ; Pie control register. Required to enable PIEPIECTRL .set 0x00000CE0 ; Pie acknowledge registerPIEACK .set 0x00000CE1 ; Pie Interrupt Enable RegistersPIEIER1 .set 0x00000CE2PIEIER2 .set 0x00000CE4PIEIER3 .set 0x00000CE6PIEIER4 .set 0x00000CE8 PIEIER5 .set 0x00000CEAPIEIER6 .set 0x00000CECPIEIER7 .set 0x00000CEE PIEIER8 .set 0x00000CF0 PIEIER9 .set 0x00000CF2PIEIER10 .set 0x00000CF4 PIEIER11 .set 0x00000CF6PIEIER12 .set 0x00000CF8; Pie Interrupt flag registersPIEIFR1 .set 0x00000CE3PIEIFR2 .set 0x00000CE5PIEIFR3 .set 0x00000CE7PIEIFR4 .set 0x00000CE9 PIEIFR5 .set 0x00000CEBPIEIFR6 .set 0x00000CEDPIEIFR7 .set 0x00000CEF PIEIFR8 .set 0x00000CF1 PIEIFR9 .set 0x00000CF3PIEIFR10 .set 0x00000CF5 PIEIFR11 .set 0x00000CF7PIEIFR12 .set 0x00000CF9
AND IER, #0x0000
AND IFR, #0x0000
//* device peripheral initialization*//
where are you placing 'sect "pievt"' in your memory?
I did not place it anywhere as such. I had just written the vector table. I learnt that the vector table is already there in ROM and after power ON it is loaded to RAM
when PIE is enabled interrupt vector table is located from 0xD00, all interrupt handlers are fetched from this offset to service respective interrupt, refer to your device system control guide -there is a table given. When PIE is disabled interrupt vector table is located in ROM, when PIE is disabled you cannot enable any interrupts shown within the PIE MAP.
I guess thats the problem, you should link your PIE Vector table to the memory begining at 0xD00. After that you will have to worry about the stack push/pop and return from isr.
But I guess it is atleast fetching the vector ID of the interrupt. As i told you I am working on timer period interrupt, I could see 0XD56 in the 0-15 bits of PIE control register.
that looks good - because you are enabling the PIE interrupt and the interrupt is getting triggered, you see those values in the register - CPU Is trying ot fetch interrupt handler at address 0xD56. But your ISR is not getting called because the handler's address is not registered in the PIE Vector table (base starting at 0xD00), once you link your PIE vector table base to address 0xD00 you will see that your interrupt is being called.
I see that you posted another question in the forum http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/t/181805.aspx - if it is the same question, can you please update if you have modified your code as suggested in this forum post. If you have already made the suggested code changes please update us with the details.
please let us know if you need more clarifications in the above.
Yes I posted the same thing in the forum. I did not make any changes from yesterday. This is how the code was written but the problem still persists. How do I link my PIE vector table with that base address. This will solve my problem completely. I have al my routines ready. I just have to integrate them into one code. I suppose you have understood my query correctly now. Thanks a lot for showing ur interest. Kindly help me with this one thing.
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