I have a design review action item to address a discrepancy in the TMS320F2812 datasheet (SPRS174T,
April 2001-Revised May 2012) concerning power up sequencing, and the power sequencing of some of
our legacy products that is using the TPS767D301 LDO. In prior revisions of the TMS320F2812 datasheet
the TPS767D301 was recommend, but has since been changed to another part.
It seems sometime in the past a engineer or consultant recommended placing a 200mSec delay
between the 3.3V and 1.9V power, and another 200mSec delay between the 1.9V and release of the
reset output (~XRS of the TMS320F2812).
In section 6.8 “Power Sequencing Requirements” Figure 6-6 implies that the core voltage (1.8/1.9V)
must be up in less than 10mSec after the I/O voltage reaches 3.3V.
The question is what are the consequences of delaying longer than 10mSec and as high as 200mSec?
The delay in holding off reset is not a concern. This can be held indefinately. The concern on holding off 1.9v power for 200ms after 3.3v power depends on how often the device enters this situation. It is a long term reliability concern so if your application, like most, is not powering on/off nemerous times a day for the lifetime of the device it is not a concern. Please advise whether your application expects to power cycle often.
Hi david i have one question, i am measuring xrs pin and i have an expected output voltage, I don't know why, I really apreciate your help.
Thanks a lot.
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