[Concerto] Alternative GPIOs for EMAC peripherals

Hi,

in our design we use EMAC with different GPIO layout than in ControlSuite v140 lwIp example. EthernetPinsSetup() was modified according to our design, but the lwIp example doesn't work. The CPU is Concerto F28M35H52C.

Q1. In lwIp example and in this (http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/p/164864/600861.aspx) different pins layout, the GPIO_O_APSEL register is not fully programmed in conjunction with PCON register, but the "spruh22.pdf" reference manual told that it should be:

"The proper bits in the Alternate Peripheral Select (GPIOAPSEL) register must be set to access these muxing options", "When these bits are set, values of 0x0 - 0xF are valid values in the GPIOPCTL PMCx bit fields."

Lwip example goes in contradiction with it. E.g.:

    // MII_TXD3
    GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
    HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) &= 0xFFF0FFFF;
    HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) |= 0x00030000;
 - APSEL not programmed for MII_TXD3

    // MII_TXCK , MII_TXEN , MII_TXD0 , MII_TXD1 , MII_TXD2 , MII_RXD0
    GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4|        GPIO_PIN_3|        GPIO_PIN_1, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet( GPIO_PORTH_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4| GPIO_PIN_3| GPIO_PIN_1, GPIO_PIN_TYPE_STD);
    HWREG(GPIO_PORTH_BASE + GPIO_O_APSEL)|= 0x000000C2;  
    HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) &= 0x00000F0F;
    HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) |= 0xCC9990C0;
- APSEL not programmed for MII_TXDn pins

and so on.

For our layout we set an APSEL bits in all places where PCTL's tetrade isn't 0, but the result in functionality is negative.
In which cases the APSEL bit should be set or not in conjunction with PCTL tetrade?

Q2. Do you test the alternate function of each available GPIO? When we used the MDIO as alt. function of the PF4_GPIO36's pin, this pin is always set to 1. But when it used as PE6_GPIO30's alt. function (as in example), it transmits some interface data. 

This initialization we used to set the MDIO on the PF4_GPIO36 pin, but got a fail.

// MDI0 RXD3
      GPIODirModeSet(GPIO_PORTF_BASE,    GPIO_PIN_4|GPIO_PIN_5,     GPIO_DIR_MODE_HW);
      GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_4|GPIO_PIN_5, GPIO_PIN_TYPE_STD);
      HWREG(GPIO_PORTF_BASE + GPIO_O_APSEL)|= 0x00000030;
      HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) &= 0xFF00FFFF;
      HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) |= 0x00330000;