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Input Qualification for TMS320x280x

Hello all,

I am planning to use the input qualification feature for the TMS320x280x according to chapter 4.4 in the reference guide  "TMS320x280x, 2801x, 2804x DSP System Control and Interrupts" (SPRU712F).

My background is the following:

I am using an input pin (GPIO) as TripZone Pin that allows me to switch off PWM signals on eg. a falling edge on the TripZone-GPIO.

Since there is a risk that this is very sensitive to glitches (due to being triggered by an edge), I want to make the functionality less sensitive by this feature of  "input qualification" (in other words: "debouncing").

According to  Table 4-4 in SPRU712F, the sampling frequency for the input qualification should calculate as follows:

 In an example of System Clock being @ 100Mhz and the register GPACTRL[QUALPRD1] = 0xFF, I obtain:

Sampling period = (2 * QUALPRD1 * TSYSCLKOUT)  =  2 * 255 * (1/100Mhz) = 5.1us   

According to SPRU712F - 4.4.3, the number of sampling periods is always one less(!) than the number of samples taken.

If the Qualification is using eg. 6 samples(GPAQSEL1.bit.GPIOxx = 2), the total sampling window width in our example should calculate as follows:

(6-1)*5.1us = 25.5us

So far so good.

If I proceed this way and I measure (on oscilloscope) the delay between the falling edge on the TripZone-GPIO and the PWM being switched off, I measure a time of approx. 35us (instead of 25.5us).

When de-activating the input qualification (= default), there is not any delay between the falling edge on TripZone and the PWM being switched off.

I repeated the measurement with a few additional settings for GPACTRL[QUALPRD1] (sample period) and GPAQSEL (3 or 6 samples taken), and in all cases, the delay between the TripZone-Event (falling edge) and the PWM being switched off was significantly greater than the time calculated as above.

In addition, I have the (unproven) impression, that the time between the falling edge on the TripZone-Pin and the deactivation of the PWM is rather

Sample Period * (number of samples +1) instead of Sample Period * (number of samples -1) (as I would read the specification).

Even if I take into account, that the falling-edge-event is asynchronous to the Sample Period, it would expect to measure a time between

Sample Period * (number of samples -1) (best-case) and

Sample Period * (number of samples) (worst-case).

I do not understand however, how the time between the two events can go up to Sample Period * (number of samples+1).

Do you have any guesses or experiences concerning the feature?

What is the error in my reasoning/arguments?

Kind regards

Christian

  • Hello,
    the calculation of the sampling frequency and total sampling window are correct. But by using GPIO as input signal it will in most cases be asynchronous to SYSCLKOUT. This could require him to provide extra time which can be calculated as follows:-
    Extra time required  =  Total sampling window + 1 SYSCLK period + 1 sampling period.
    This is mentioned in NOTE: pg 78 of SPRUFN3D.