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SEQ1/2_BSY register on F281x

Maite
Prodigy 330 points

Hi champs,

My customer is aware of the INT_SEQ1/2 errata on F281x devices. They are not using the INT_SEQ1/2 registers but SEQ1/2_BSY regs instead. They are wondering if the same 1 extra cycle delay will apply to the SEQ1/2_BSY since they are not using INT_SEQ1/2.

Thanks,

 Maite

  • 0
    TI__Prodigy 330 points

    Hi again,

    Regarding the question below, since the errata only talks about INT_SEQ1/2, can I assume that they don't need to consider any extra delay if they are not using the specified register?

    Cheers,

    Maite 

  • 0 in reply to Maite
    TI__Guru 71835 points

    Maite,

    This is correct, there is no errata concerning the BSY bits.  Only disadvantage to using the BSY bits is they have to be polled, rather than wait for a PIE Interrupt as with the INT_SEQ1/2 bits.  If customer was polling the SEQ1/2 anyway than this is a non-issue.

     

    Best,

    Matthew