I am using the phase shift technique to control a DC/DC converter.
I have configured PWM1 as a master and PWM2, 3 and 4 as slaves. To control the phase of PWM, I set TBPHS register with the appropiate value.
The problem I am facing is the following:
The delay of PWM3 sometimes is positive and sometimes is negative. When I change the phase from a negative value to a positive value, the peripheric mantains the PWM output in on position for a complete period before it updates the phase of the PWM.
I am adding the peripheral configuration.
Thank you in advance
// PAREM ELS CLOCKS DELS ePWM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
// CONFIGURACIÓ REGISTRE TBCTL
EPwm1Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm3Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm4Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
// CONFIGURACIÓ REGISTRE TBPHS
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm2Regs.TBPHS.half.TBPHS = 0;
EPwm3Regs.TBPHS.half.TBPHS = 0;
EPwm4Regs.TBPHS.half.TBPHS = 0;
// CONFIGURACIÓ DE LA RECARGA DELS REGISTRES DE COMPARACIÓ
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//CONFIGUREM PERÍODE, MODULADORA
EPwm1Regs.TBPRD = T_CONM;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm2Regs.TBPRD = T_CONM;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm3Regs.TBPRD = T_CONM;
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm4Regs.TBPRD = T_CONM;
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
// HABILITEM I CONFIGUREM SOC DEL ADC
EPwm1Regs.ETSEL.bit.SOCAEN = ENABLE_BIT;
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
// HABILITEM I CONFIGUREM INTERRUPCIÓ DEL ePWM 1 i 5
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;
EPwm1Regs.ETSEL.bit.INTEN = ENABLE_BIT;
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;
//INICIALITZACIÓ DELS DUTIES
EPwm1Regs.CMPA.half.CMPA = duty50;
EPwm2Regs.CMPA.half.CMPA = duty50;
EPwm3Regs.CMPA.half.CMPA = duty50;
EPwm4Regs.CMPA.half.CMPA = duty50;
EPwm1Regs.CMPB = duty50;
EPwm2Regs.CMPB = duty50;
EPwm3Regs.CMPB = duty50;
EPwm4Regs.CMPB = duty50;
// ESPECIFICA CONMUTACIÓ DE LES SORTIDES PWM
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.IN_MODE = DBB_ALL;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm1Regs.DBFED = TEMPS_MORT;
EPwm1Regs.DBRED = TEMPS_MORT;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.IN_MODE = DBB_ALL;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm2Regs.DBFED = TEMPS_MORT;
EPwm2Regs.DBRED = TEMPS_MORT;
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.IN_MODE = DBB_ALL;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm3Regs.DBFED = TEMPS_MORT;
EPwm3Regs.DBRED = TEMPS_MORT;
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm4Regs.DBCTL.bit.IN_MODE = DBB_ALL;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm4Regs.DBFED = TEMPS_MORT;
EPwm4Regs.DBRED = TEMPS_MORT;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced
EDIS;