This is for the TMS320F2833X.
When interrupt happens, what information does the "context save" save? Some reference guide says it automatically save some basic registers in 6 to 7 cycles. However, it does not save RB register and the floating CPU related registers. It's the ISR responsibility to save above information. All the floating registers have shadow registers. If nested interrupt is not supported, then the floating registers can be saved in the shadow registers when entering the ISR. If nested interrupt is supported, the floating registers have to be pushed to the stack. In the worst case, it is said the context save may cost more than 40 cycles. Can anybody clarify above issues?
Also, has anybody has the RTOS experience with delfino processor? TI says they have the RTOS support for ARM M4 processors. Does TI support RTOS implementation for delfino and Piccolo processors?
Thanks.