This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MCBSP XRDY not set , XSR registers not emptied ??

Hi,

I am experiencing some trouble with MCBSP peripheral. It is configured in TX mode, frame-sync. Frame and CLK are externally provided.

What I see is that ISR (XINTM = 0, Interrupt request when XRDY is set) occurs only after the Init, when XRST is set.

after that, even if I write new data in the DXR registers, no new data are sent trough the MDXB pin (no bistream on the oscilloscope).

I have the feeling that somehow the XSR registers are not emptied, preventing XRDY to be set again (correct?).

Frame-sync pulse and CLK are externally provided. CLK is active only when Frame-sync is high.

these are the settings of the peripherals:

//*************** RESET MCBSP
McbspbRegs.SPCR2.bit.FRST=0; // Frame Sync generator reset
McbspbRegs.SPCR2.bit.GRST=0; // Sample Rate generator Reset
McbspbRegs.SPCR2.bit.XRST=0; // Transmitter reset
McbspbRegs.SPCR1.bit.RRST=0; // Receiver reset

//*************** Initialize McBSP Registers
McbspbRegs.SPCR2.all=0x0000; // XRST =0
McbspbRegs.SPCR1.all=0x0000; // RRST =0, DLB disabled

McbspbRegs.RCR2.all=0x0000; // RDATDLY = 0
McbspbRegs.RCR2.bit.RDATDLY = 0x1; // 1-bit data delay

McbspbRegs.RCR1.bit.RWDLEN1=0x4; // RWDLEN1 = 24bit, 1 word in rcv. frame
McbspbRegs.XCR2.all=0x0000;
McbspbRegs.XCR1.all=0x0;


McbspbRegs.XCR1.bit.XWDLEN1 = 0x5; // word length = 32bit
McbspbRegs.XCR1.bit.XFRLEN1 = 0x5; // 6 word per frame

McbspbRegs.MCR2.all=0x0;
McbspbRegs.MCR1.all=0x0;

McbspbRegs.PCR.bit.CLKXM = 0x0; // external clock source from MCLKXB pin

delay_loop();

McbspbRegs.SPCR1.bit.CLKSTP = 0; // clk-stop mode disabled
McbspbRegs.PCR.bit.CLKXP = 0x1; // sampling on falling edge
McbspbRegs.PCR.bit.CLKRP = 0x1; // sampling on falling edge

McbspbRegs.PCR.bit.FSXM = 0x0; // FSX is created externally
McbspbRegs.PCR.bit.FSXP = 0x0; // Transmit frame-synchronization pulses are active high

McbspbRegs.SPCR2.bit.XINTM = 0x0; // IRQ when frame syn pulse

//************* Enable Sample rate generator

clkg_delay_loop(); // Wait at least 2 SRG clock cycles


McbspbRegs.MFFINT.bit.XINT = 1; // enable interrupts
McbspbRegs.SPCR2.bit.XRST=1; // release TX from reset

Does anyone have an idea of what is happening? why there is not TX bitstream and/or XSR registers seem to be not emptied?

any suggestion is really appreciated.

Thanks