F28M35H52C1- EPI's ALE Pin Ideal State

Hi,

   I am using the above controller. I am using the EPI communication to my SRAM. 

My configuration is HB8 mode with address and Data lines muxed. And using ALE with dual chip select. From the Tech datasheet "Concerto F28M35x Technical reference" 

pag no.: 1356 ( Figure 19-9), ALE( EPI0S30 ) line IDEAL state is LOW. But my configuration I am getting Inverted output.

My ALE line IDEAL state is HIGH. While sending the address, ALE went to LOW. 

My code is Below:

void
SetPortControl(void)
{
//
// GPIO Port C pins
//

HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) = GPIO_PCTL_PC4_EPI0S2 |
GPIO_PCTL_PC5_EPI0S3 |
GPIO_PCTL_PC6_EPI0S4 |
GPIO_PCTL_PC7_EPI0S5;

//
// GPIO Port D pins
//
HWREG(GPIO_PORTD_BASE + GPIO_O_PCTL) = GPIO_PCTL_PD7_EPI0S30 |
GPIO_PCTL_PD6_EPI0S29 ;

//
// GPIO Port H pins
//
HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) = GPIO_PCTL_PH0_EPI0S6 |
GPIO_PCTL_PH1_EPI0S7 |
GPIO_PCTL_PH2_EPI0S1 |
GPIO_PCTL_PH3_EPI0S0 ;

HWREG(GPIO_PORTJ_BASE + GPIO_O_PCTL) = GPIO_PCTL_PJ4_EPI0S28 ;
}

void EPI_LCD_COMM_Init()
{

// Enable Clock for EPI & GPIO Ports
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);

// Configure the GPIO setting for the EPI pins.
SetPortControl();

GPIODirModeSet(GPIO_PORTC_BASE,
(GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7),
GPIO_DIR_MODE_HW);

GPIOPadConfigSet(GPIO_PORTC_BASE,
(GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7),
GPIO_PIN_TYPE_STD_WPU);

GPIODirModeSet(GPIO_PORTD_BASE,
(GPIO_PIN_6 | GPIO_PIN_7 ),
GPIO_DIR_MODE_HW);

GPIOPadConfigSet(GPIO_PORTD_BASE,
(GPIO_PIN_6 | GPIO_PIN_7),
GPIO_PIN_TYPE_STD_WPU);

GPIODirModeSet(GPIO_PORTH_BASE,
(GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_DIR_MODE_HW);

GPIOPadConfigSet(GPIO_PORTH_BASE,
(GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_PIN_TYPE_STD_WPU);

GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_4 , GPIO_DIR_MODE_HW);

GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_4 , GPIO_PIN_TYPE_STD_WPU);

// Set 8 Bit HostBus mode.
EPIModeSet(EPI0_BASE, EPI_MODE_HB8);

//Set clock divider to 1 (divide by 2). With this EPI Frq will be 37.5MHz (M3-Frq/2).
EPIDividerSet(EPI0_BASE, 0x1);

// Read wait state = 0
// Write wait state = 0
// Address & Data are not muxed (ADNOMUX = 0x1).
EPIConfigHB8Set(EPI0_BASE, (EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_0 | EPI_HB8_RDWAIT_0), 0);

EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_PER_SIZE_64KB | EPI_ADDR_RAM_SIZE_64KB | EPI_ADDR_RAM_BASE_6 | EPI_ADDR_PER_BASE_A) );

GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_5);
GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_5, ~0);
GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, GPIO_PIN_7);
GPIOPinWrite(GPIO_PORTG_BASE, GPIO_PIN_7, ~0);
GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_7);
GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_7, ~0);
// word access mode enabled.
// EPI0S30 is used as CSn/CEn
HWREG(EPI0_BASE + EPI_O_HB8CFG2) = 0x03000000;

}

int
main(void)
{
volatile unsigned long ulLoop;
// Disable Protection
HWREG(SYSCTL_MWRALLOW) = 0xA5A5A5A5;

// Sets up PLL, M3 running at 100MHz and C28 running at 100MHz
SysCtlClockConfigSet(SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 0xA) |
SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_1 |
SYSCTL_XCLKDIV_4);

// Disable clock supply for the watchdog modules
SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);
SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);

// Enable processor interrupts.//
IntMasterEnable();
EPI_LCD_COMM_Init();

while(1)
{
SRAM_Write_Data();
for(ulLoop = 0;ulLoop<15000;ulLoop++);
}
}

void
SRAM_Write_Data()
{
unsigned int Data = 0x01;
short *MemLoc = (short *)(0x60000000);
*MemLoc = Data;
}

Thanks 

Thirumoorthy.R