The processor TMS320F28034 worked by using the OSC1CLK for the PLL very well!
We tried to activate the external clock from GPIO38, but in this mode the PLL worked only in bypass-configuration. After this we switched OSCCLKSRC2 to 1 (working with OSC2CLK). For this the PLL worked in bypass-configuration too.
Please tell us how we can activate the external Clock EXTCLK (7,5 MHz)! Thanks.
Our Software:
//---------------------------------------------------------------------------
// Internal 10MHz-Osczillator 1
//---------------------------------------------------------------------------
// This function switches to OSC1CLK and turns off all other clock
// sources to minimize power consumption.
// DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT (interner 10MHz --> 60MHz)
// DSP28_PLLCR 12 // Uncomment for 60 MHz devices [60 MHz = (10MHz * 12)/2]
void IntOsc1Sel (void) {
EALLOW;
SysCtrlRegs.XCLK.bit.XCLKINSEL = 0; // 1-GPIO19 = XCLKIN, 0-GPIO38 = XCLKIN
// Auswahl GPIO38 (Pin 45) als ext. Clock
SysCtrlRegs.CLKCTL.bit.XTALOSCOFF = 1; // Turn off XTALOSC / external Crystal XTAL off
SysCtrlRegs.CLKCTL.bit.XCLKINOFF = 1; // Turn off XCLKIN
SysCtrlRegs.CLKCTL.bit.OSCCLKSRC2SEL = 0; // Switch to external clock
SysCtrlRegs.CLKCTL.bit.OSCCLKSRCSEL = 0; // interner Osc1
SysCtrlRegs.CLKCTL.bit.WDCLKSRCSEL = 0; // Switch Watchdog Clk Src to internal clock OSC1CLK
SysCtrlRegs.CLKCTL.bit.INTOSC2OFF = 1; // Turn off INTOSC2
SysCtrlRegs.CLKCTL.bit.INTOSC1OFF = 0; // Turn on INTOSC1
SysCtrlRegs.CLKCTL.bit.INTOSC1HALTI = 1; // Osc1 ignore HALT
SysCtrlRegs.CLKCTL.bit.TMR2CLKSRCSEL = 2; // Osc1 für CPU-Timer2-Clock
SysCtrlRegs.CLKCTL.bit.TMR2CLKPRESCALE = 0; // Div 1 für CPU-Timer2
EDIS;
}
#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT (externer 7,5MHz --> 60MHz)
#define DSP28_PLLCR 8 // Uncomment for 60 MHz devices [60 MHz = (7,5MHz * 8)/1]
//---------------------------------------------------------------------------
// Example: ExtOscSel: XCLKIN (7,5MHz)
//---------------------------------------------------------------------------
// This function switches to external Clock XCLKIN an GPIO38 (Pin 45)
// and turn on the oscillator 1 for clocking the CPU-Watchdog.
// Clock Control Register CLKCTL (all Bits 0 after Reset! Read and write)
// DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT (external 7,5MHz --> 60MHz)
// DSP28_PLLCR 8 // Uncomment for 60 MHz devices [60 MHz = (7,5MHz * 8)/1]
void ExtOscSel (void) {
EALLOW;
SysCtrlRegs.XCLK.bit.XCLKINSEL = 0; // 1-GPIO19 = XCLKIN, 0-GPIO38 = XCLKIN
SysCtrlRegs.CLKCTL.bit.XTALOSCOFF = 1; // Turn off XTALOSC / external Crystal XTAL off
SysCtrlRegs.CLKCTL.bit.XCLKINOFF = 0; // Turn on XCLKIN (7,5MHz Takt)
SysCtrlRegs.CLKCTL.bit.OSCCLKSRC2SEL = 0; // Switch to external clock
//SysCtrlRegs.CLKCTL.bit.OSCCLKSRC2SEL = 1; // Switch to OSC2 clock
SysCtrlRegs.CLKCTL.bit.OSCCLKSRCSEL = 1; // external Clock von XCLKIN or XTAL
//SysCtrlRegs.CLKCTL.bit.OSCCLKSRCSEL = 0; // interner Clock von OSC1
//SysCtrlRegs.CLKCTL.bit.WDCLKSRCSEL = 0; // Switch Watchdog Clk Src to internal clock OSC1CLK
SysCtrlRegs.CLKCTL.bit.WDCLKSRCSEL = 1; // Switch Watchdog Clk Src to external clock EXTCLK
//SysCtrlRegs.CLKCTL.bit.INTOSC2OFF = 0; // Turn on INTOSC2
SysCtrlRegs.CLKCTL.bit.INTOSC2OFF = 1; // Turn off INTOSC2
SysCtrlRegs.CLKCTL.bit.INTOSC2HALTI = 1; // Osc2 ignore HALT
//SysCtrlRegs.CLKCTL.bit.INTOSC1OFF = 0; // Turn on INTOSC1 for clocking the WD
SysCtrlRegs.CLKCTL.bit.INTOSC1OFF = 1; // Turn off INTOSC1
SysCtrlRegs.CLKCTL.bit.INTOSC1HALTI = 1; // Osc1 ignore HALT
SysCtrlRegs.CLKCTL.bit.TMR2CLKSRCSEL = 0; // SYSCLOCKOUT (60MHz) for CPU-Timer2-Clock
//SysCtrlRegs.CLKCTL.bit.TMR2CLKSRCSEL = 1; // EXTCLK (60MHz) for CPU-Timer2-Clock
//SysCtrlRegs.CLKCTL.bit.TMR2CLKSRCSEL = 2; // Osc1 for CPU-Timer2-Clock
//SysCtrlRegs.CLKCTL.bit.TMR2CLKSRCSEL = 3; // Osc2 for CPU-Timer2-Clock
SysCtrlRegs.CLKCTL.bit.TMR2CLKPRESCALE = 0; // Div 1 für CPU-Timer2
EDIS;
}
//---------------------------------------------------------------------------
// Example: InitPll:
//---------------------------------------------------------------------------
// This function initializes the PLLCR register.
void InitPll(Uint16 val, Uint16 divsel)
{
volatile Uint16 iVol;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
EALLOW;
// OSCCLKSRC1 failure detected. PLL running in limp mode.
// Re-enable missing clock logic.
SysCtrlRegs.PLLSTS.bit.MCLKCLR = 1;
EDIS;
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
asm(" ESTOP0"); // Uncomment for debugging purposes
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
// This puts us in 1/4
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
// Change the PLLCR
if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
//SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop, or fed within
// the loop via ServiceDog().
// Uncomment to disable the watchdog
DisableDog();
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
EALLOW;
SysCtrlRegs.PLLCR.bit.DIV = val;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
// If switching to 1/2
if((divsel == 1)||(divsel == 2))
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
EDIS;
}
// If switching to 1/1
// * First go to 1/2 and let the power settle
// The time required will depend on the system, this is only an example
// * Then switch to 1/1
if(divsel == 3)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
DELAY_US(50L);
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
EDIS;
}
}
Best Regards and thank you very much for your Help,
Waldemar