TMS320F28335 Clock configuration problem

Hai all,

Case1:

We are bypassing the PLL using the configuration : SysCtrlRegs.PLLCR.bit.DIV = 0;

                                                                                        SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;

Oscillator input is 30MHz and the output observed at XCLKOUT as 30MHz(at TP2 in the EzDSP F28335 eval board).

Now by enabling PLL as SysCtrlRegs.PLLCR.bit.DIV = 10;
                                           SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;

Case 2  :

// XTIMCLK = SYSCLKOUT/2
   XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
   // XCLKOUT = XTIMCLK/2
   XintfRegs.XINTCNF2.bit.CLKMODE = 1;
   // Enable XCLKOUT
   XintfRegs.XINTCNF2.bit.CLKOFF = 0;

The Oscillator input is 30MHz and the output observed at XCLKOUT as 37.5MHz by configuring the above registers which is expected output clock.

Case 3:

    // XTIMCLK = SYSCLKOUT/1
   XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
   // XCLKOUT = XTIMCLK/1
   XintfRegs.XINTCNF2.bit.CLKMODE = 0;
   // Enable XCLKOUT
   XintfRegs.XINTCNF2.bit.CLKOFF = 0;

The Oscillator input is 30MHz and the output observed at XCLKOUT as 37.5MHz by configuring the above registers which is not expected output clock. 150MHz is the expected output at XCLKOUT with the above configuration.

External clock oscillator used is 30MHz and by using the Internal PLL configuration we generated the clock as 150MHz

Could you please help us with the configuration of clock to generate 150MHz?

On which clock the CPU core(F28335) will be running on?

With the following configuration, CPU is expected to run on the SYSCLKOUT(150MHz), one instruction cycle should take 6.67ns.

But with this configuration, it is running on SYSCLKOUT as 37.5MHz which is calculated by Toggling a GPIO pin which takes 8.33MHz clock observed on the oscilloscope.

Now by enabling PLL as SysCtrlRegs.PLLCR.bit.DIV = 10;
                                           SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;

Please reply ASAP.

Thanks,

Lakshmi.