Dear all:
I am working on a project that the ADC Sample is triggered by epwm1 at 350kHZ, and EOC0 trigger the CLAINT1, I read the ADCRESULT0 in the cla isr. I have found the result is unstabled. when I set the SOCAPRD = 2, the result is stabled.
Is it the sample frequency too high?Here is my part of code. Please help me figure out.
void InitAdc(void)
{
extern void DSP28x_usDelay(Uint32 Count);
// *IMPORTANT*
// The Device_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
(*Device_cal)();
EDIS;
// To powerup the ADC the ADCENCLK bit should be set first to enable
// clocks, followed by powering up the bandgap, reference circuitry, and ADC core.
// Before the first conversion is performed a 5ms delay must be observed
// after power up to give all analog circuits time to power up and settle
// Please note that for the delay function below to operate correctly the
// CPU_RATE define statement in the DSP2803x_Examples.h file must
// contain the correct CPU clock period in nanoseconds.
EALLOW;
AdcRegs.ADCCTL1.bit.ADCREFSEL = 0; // Select interal BG
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power ADC BG
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // Enable ADC
EDIS;
DELAY_US(ADC_usDELAY); // Delay before converting ADC channels
// Configure ADC
EALLOW;
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 1; //Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 0; //setup EOC0 to trigger ADCINT1 to fire
//AdcRegs.SOCPRICTL.bit.SOCPRIORITY = 2; //SOC0,SOC1,SOC2 ,SOC3and SOC4 are high priority
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0x1; //set SOC0 channel select to ADCINA1 (V_PI_OUT)
AdcRegs.ADCSOC1CTL.bit.CHSEL = 0x2; //set SOC1 channel select to ADCINA2 (I_PI_OUT)
AdcRegs.ADCSOC2CTL.bit.CHSEL = 0x3; //set SOC2 channel select to ADCINA3 (VO)
AdcRegs.ADCSOC3CTL.bit.CHSEL = 0x4; //set SOC3 channel select to ADCINA4 (IO)
AdcRegs.ADCSOC4CTL.bit.CHSEL = 0x6; //set SOC4 channel select to ADCINA6 (REF_2V5)
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x7; //set SOC5 channel select to ADCINA7 (V3.3)
AdcRegs.ADCSOC6CTL.bit.CHSEL = 0x8; //set SOC6 channel select to ADCINB0 (12VS)
AdcRegs.ADCSOC7CTL.bit.CHSEL = 0x9; //set SOC7 channel select to ADCINB1 (5VS)
AdcRegs.ADCSOC8CTL.bit.CHSEL = 0xA; //set SOC8 channel select to ADCINB2 (TEMP_HOT)
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 0x5; //set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0x5; //set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 0x5; //set SOC2 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 0x5; //set SOC3 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 0x5; //set SOC4 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 0x5; //set SOC5 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC6CTL.bit.TRIGSEL = 0x5; //set SOC6 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC7CTL.bit.TRIGSEL = 0x5; //set SOC7 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC8CTL.bit.TRIGSEL = 0x5; //set SOC8 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;//set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;//set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;//set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;//set SOC3 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;//set SOC4 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;//set SOC5 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC6CTL.bit.ACQPS = 6;//set SOC6 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC7CTL.bit.ACQPS = 6;//set SOC7 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC8CTL.bit.ACQPS = 6;//set SOC8 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
// Assumes ePWM6 clock is already enabled in InitSysCtrl();
EPwm1Regs.ETSEL.bit.SOCAEN = 1;// Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 1;// Enable event time-base counter equal to CMPA. (TBCTR = 0x0000)
EPwm1Regs.ETPS.bit.SOCAPRD = 2; // Generate pulse on 1st ev
EDIS;
// Wait for ADC interrupt
DSP28x_usDelay(100);
}
