Dear all,
In the frame of a R&D project, I need to use up to 2 C28346 ControlCard as SPI slaves. Each of the ControlCard is attached through the DIMM168 connector to a home-made PCB on which are the powersupplies and so on. The home-made PCB also takes care of the SPI slaves connection: A master board sends, through a flat cable, the SPI signals to the first slave board where they goes to the DIM168 connector and to the second slave board, also through a flat cable.
I am using the SPId module of the C28346 on pins shared with GPIO 48 to 51. the configuration is as follows:
//----------------------------- SPI D---------------------------------------------
// Used to communicate with the CPU (master board)
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBPUD.bit.GPIO48 = 1; // Disable pull-up on GPIO48 (SPISIMOD)
GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (SPISOMID)
GpioCtrlRegs.GPBPUD.bit.GPIO50 = 1; // Disable pull-up on GPIO50 (SPICLKD)
GpioCtrlRegs.GPBPUD.bit.GPIO51 = 1; // Disable pull-up on GPIO51 (SPISTED)
/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // Asynch input GPIO48 (SPISIMOD)
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // Asynch input GPIO49 (SPISOMID)
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // Asynch input GPIO50 (SPICLKD)
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // Asynch input GPIO51 (SPISTED)
/* Configure SPI-D pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SPI functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // Configure GPIO48 as SPISIMOD
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // Configure GPIO49 as SPISOMID
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // Configure GPIO50 as SPICLKD
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // Configure GPIO51 as SPISTED
/* Configure GPIO37 for be high to put the SRAM mounted on the controlboard in power-down mode
in order to avoid conflict with SPI signals*/
GpioCtrlRegs.GPBPUD.bit.GPIO37 = 1; // Disable pull-up on GPIO37 (nCE_H)
GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 3; // asynchronous GPIO37
GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1; // GPIO37 is an output
GpioDataRegs.GPBSET.bit.GPIO37 = 1; // GPIO37 is HIGH
SpidRegs.SPICCR.bit.SPISWRESET = 0; // Reset SPId during configuration
SpidRegs.SPICCR.bit.CLKPOLARITY = 0; // Data output @ rising edge and input @ falling edge (CLK_POLARITY = 0)
SpidRegs.SPICTL.bit.CLK_PHASE = 0; //
SpidRegs.SPICCR.bit.SPICHAR = 15; // data transmitted in 16 bits
SpidRegs.SPICTL.bit.OVERRUNINTENA = 0; // Disable receiver overrun interrupt
SpidRegs.SPICTL.bit.MASTER_SLAVE = 0; // configured as a slave
SpidRegs.SPICTL.bit.TALK = 1; // Enable transmission
SpidRegs.SPICTL.bit.SPIINTENA = 0; // SPId interrupts disabled
SpidRegs.SPIBRR = 14; // LSPCLK = 75 MHz
// SPICLK = 75 MHz /(14+1) = 5 MHz
SpidRegs.SPIPRI.bit.SOFT = 1; // Free run
SpidRegs.SPIPRI.bit.FREE = 1;
SpidRegs.SPICCR.bit.SPISWRESET = 1; // End of configuration
SpidRegs.SPICTL.bit.SPIINTENA = 1; // Enables SPId interrupts
PieVectTable.SPIRXINTD = &SpiInterrupt; // Map the SPI_D RX interrupt to the ISR
PieCtrlRegs.PIEIER6.bit.INTx7 = 1; // Enables SPIRXTINTD in the PIE: Group 6 interrupt 1
IER |= M_INT6; // Enable interrupts from group 6
EDIS;
So far so good, but here is my issue: When I am using only one SPI slaves, everything goes perfectly well. But as soon as I connect a second SPI slave board, the communication between the master board and the first salve, and only the first one, goes bad. The first slave seems to skip bits and therefore does a lot of bad things with the received information.
I have already spent a lot of time on this issue (almost 2 weeks) and I am reaching the end of my time budget. So has anyone already experienced something like that???
I have already been able to rule out few possible explanations:
a) I exchanged the physical boards (Slave 2 goes to slot 1 and Slave 1 to slot 2) => same result
b) I decrease the clk speed down to 10 kHz => same result
c) I checked every single signals of the SPI bus on both slave boards (on the DIMM168 connectors) => can't find anything wrong (the edges are steep, the logical levels well defined, the timing adapted)
d) I have seen that the SPId pins I am using are shared with a Flash memory (U20) on the ControlCard. I put the memory pins in high-z state by putting C28346 GPIO37 HIGH => same results. I unsoldered U20 => same results
e) I connected both slave boards but talked only to the first one => same results
f) I changed the connecting flat cables => same results
g) I changed the ControlCards => same results
h) I connected both home-made slave boards but with no ControlCard on the second => the communication goes well again but that doesn't really solve my problem since I can't use both at the same time.
Therefore, I have been able to determine that the issue it related to the ControlCard itself and to my home-made hardware, since connecting a second ControlCard puts the first one into trouble.
Nevertheless, I have not been able to figure out what is wrong as, since I unsoldered U20 on the ControlCard, the SPI signals are not shared with anything else than the C28346! I have looked in the silicon errata but was unable to find any problem related to SPId.
I can provide the hardware layout and schematics by e-mail but I don't want to broadcast them on the net.
My next step is move the SPId to SPIa pins (GPIO 16 to GPIO19), which are not shared with anything else on the ControlCard and use buffer to "isolate" the slaves from one-another. Nevertheless, hardware changes are time consuming and I wanted to make sure it is the only solution.
So please, does anyone have a idea?
Many thanks in advance to anyone able to help me :)
Christian
