Piccolo F28069 interrupts

Hi Tom,

This is possible in a few ways.

Using CPU interrupts directly is certainly possible, but it may use a good chunk of the CPU bandwidth.  The ISR latency for external interrupts is 16 cycles. (http://processors.wiki.ti.com/index.php/Interrupt_FAQ_for_C2000).  

You could also use the eCAP peripheral to count the number of clock cycles between edges to determine the frequency directly (or the HRCAP module to determine the frequency directly with resolution higher than the system clock).  I think it is also possible to use the eCAP as a /2 to /4 pre-scale to reduce interrupt frequency.  I think using eCAP as a pre-scale (even at /1) also would allow you to use offload the counting to the CLA co-processor instead of using the CPU.

If you use the internal oscillators instead of crystal or external clock (red path), you can feed one signal to the XCLKIN input on GPIO19 or GPIO38 and then count the edges with CPUTIMER2 (green path).

Hi Tom,

You've not mentioned which interrupts are talking about software or hardware:

Here's data for external interrupts:

8 CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events.

Regards,

Gautam