Concerto IPC and Shared memory problem in m3 processor

Ali,

did you configure the shared memory ownership properly from M3 before?

Best Regards

Santosh

Hi Ali,

Just to add what Santosh has mentioned, the write and execute permission for shared RAM depends on which subsystem has the master ownership of a specific shared RAM block. By default M3 has the master ownership of all shared RAM blocks which means M3 will have all the accesses but C28x will only have READ access. User need to change the master ownership to C28x if application need to have WRITE/EXECUTE permission for any of the shared RAM block. Please refer the definition of MSxMSEL register in TRM for more detail on this.

Regards,

Vivek Singh

I have assigned the ownership to C28 by this:

RAMMReqSharedMemAccess((S0_ACCESS | S1_ACCESS),C28_MASTER);

The data is stored in a structure:

extern struct SharedMemoryStructureSlaveToMaster

{

float VdcSet;

unsigned int ControlActive;

unsigned int SendPhaseInitFlag;

} SharedMemoryS2M;

Then in source file I have: 

struct    SharedMemoryStructureSlaveToMaster    SharedMemoryS2M;

 #pragma DATA_SECTION(SharedMemoryS2M,"SHARERAMS0");

In the C28 side, all data are good but in m3 side, all the time it reads '0'

 

Ali,

M3 would read 0s on shared RAM S0 because M3 gave ownership of that shared RAM to C28x. It will have to regain the ownership before it can read the data in shared RAM S0.

 

Best Regards

Santosh

 

looks like the below is not true, vivek corrected me saying M3 should be able to read even when C28x owns the shared RAM, lets wait for Vivek to confirm whats going on here.

Santosh Athuru said:

M3 would read 0s on shared RAM S0 because M3 gave ownership of that shared RAM to C28x. It will have to regain the ownership before it can read the data in shared RAM S0.

 

Best Regards

Santosh

Hi Ali,

After loading the code on C28x, please try to open the same address location in CCS Memory Watch Window from M3 and see if it's showing the correct data.

Please note that the address for S0 Shared RAM on M3 and C28x are different.

M3     -   0x20008000 – 0x2000 9FFF

C28x -   0xC000 – 0xCFFF

Regards,

Vivek Singh 

Hi,

I tested the memory browser. C28 has not problem just as I mentioned. 

The problem is all with m3. The memory at sharedrams0 does not get updated. it takes a value and never updates.

Hi Ali,

Is the issue you were facing is resolved?

Regards,

Vivek Singh

Hi,

No, the problem has not solved yet. I don't know what I should do.

Hi Ali,

Do you have another device where you could try the same program?

Regards,

Vivek Singh

Hi,

I have tried different control cards too, but the same problem exist.

I always use the on board JTAG interface to debug the system.

Thanks

Hi Ali,

Is it possible for you to send us the sample code which has this issue?

Regards,

Vivek Singh

Hi Vivek,

Sorry for the delay.

I've attached the source code I use for both C28 and M3 processor.

Best regards

Hi Vivek,

Did you checked the code? Did you get the same result?

I've worked a lot on the code but find nothing suspicious about it.

Thanks

Hi Ali,

Sorry for late response!!

Yes, I executed the code your sent. I don't know how to check test has passed or not but I did check the values of variable updated by C28x in S0 memory space from M3 debugger and I see them getting updated correctly. I checked the variable "SharedMemoryS2M.VdcSet" (@0xC000 on C28x) and when I open the same location on M3 side (0x20008000), I could see it's getting updated.

Regards,

Vivek Singh

 

Hi,
I have some questions:

1- Did you used the onboard debugger of the concerto control card?

2- Did the values in memory section SharedMemoryS2M.VdcSet get updated continuously?

Thanks

Hi Ali,

Did you managed to get it working?

Looks like I have similar issue here.

Cheers,

Hi Mohsen,

I couldn't fix the problem. I tried a lot of ways to make it running but they didn't work. 

Thanks

Hi Ali,
I think I know what the problem was for my case.
the memory map in two CPUs where not aligned. if you refer to the F28M36x Concerto™ Microcontrollers datasheet page 16:
2000 8000 – 2000 9FFF S0 RAM (Parity, Shared) 8K 0000 C000 – 0000 CFFF
2000 A000 – 2000 BFFF S1 RAM (Parity, Shared) 8K 0000 D000 – 0000 DFFF
2000 C000 – 2000 DFFF S2 RAM (Parity, Shared) 8K 0000 E000 – 0000 EFFF
2000 E000 – 2000 FFFF S3 RAM (Parity, Shared) 8K 0000 F000 – 0000 FFFF
2001 0000 – 2001 1FFF S4 RAM (Parity, Shared) 8K 0001 0000 – 0001 0FFF
2001 2000 – 2001 3FFF S5 RAM (Parity, Shared) 8K 0001 1000 – 0001 1FFF
2001 4000 – 2001 5FFF S6 RAM (Parity, Shared) 8K 0001 2000 – 0001 2FFF
2001 6000 – 2001 7FFF S7 RAM (Parity, Shared) 8K 0001 3000 – 0001 3FFF
the shared memory area is addressed differently in to CPUs.
In C28 step sizes are 0x1000 e.g. C000,D000,...
In M3 step sizes are 0x2000 e.g. 2000 8000,2000 A000,...
I hope it helps...