I have a very basic question on the Digital Compare submodule. I have read the description in the PWM document 10 times and it is still not obvious to me what the significance of the 'H' and 'L' designations on DCAH, DCAL, DCBH and DCBL signals are. Does this imply an edge triggered event, with H and L specifying which edge triggers the event?
I need to to do the following:
1) Use DCAEVT1.sync to load phase value into EPM1 time base counter on the falling edge of one of the internal comparator inputs or the falling edge of EPM2A low edge (these are two distinct different operating modes, configuration would change based on certain external conditions determined by software). In the case of using the falling edge of EPWM2A I guess I would connect to one of the TZ1-TZ3 inputs.
2) Drive EPWM1B low on the falling edge of another internal comparator input cycle by cycle.
3) Drive both EPWM1A and EPWM1B low on another TZ input, can be configured either pos or neg edge, cycle by cycle (overcurrent protection).
4) Drive both EPM1A and B low on the third TZ input on a latch basis (ov protection or hard overcurrent).
Probably need some filtering or blanking on some or all of these events.