Hi,
i'm using TMS320F28027 controller to drive a dc motor. my PWM generation table is given below, first the C signal should be in ON condition and in next stage C and D should be in ON condition and then only D should be in ON condition like wise the sequence goes. I need to create the sequence of signals like c, cd ,d,da,a,ab,b, bc ,again c , i tried this and i'm getting only sequence of signals as c,cd,d,da,a,ab and c so i need to know how this b,bc sequence can be generated. can any body guide me how to create the fourth sequence???
Program:
#include "DSP28x_Project.h"
#include "F2802x_Device.h"
void epwm_init(void);
void epwm_init_1(void);
void epwm_init_2(void);
void epwm_init_3(void);
int main(void)
{
InitGpio();
InitSysCtrl();
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
epwm_init();
epwm_init_1();
epwm_init_2();
epwm_init_3();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A)
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B)
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
EDIS;
while(1);
}
void epwm_init(void)
{
EPwm1Regs.TBPRD = 60000; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUTTB_COUNT_DOWN
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm1Regs.TBCTL.bit.SYNCOSEL=TB_SYNC_IN;
//EPwm1Regs.TBCTL.bit.SYNCOSEL=TB_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
// EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm1Regs.CMPA.half.CMPA = 15000;
// EPwm1Regs.CMPB = 15000;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
}
void epwm_init_1(void)
{
EPwm2Regs.TBPRD = 60000; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 40000;
EPwm2Regs.TBCTL.bit.PHSEN=1;
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.SYNCOSEL=TB_SYNC_IN;
// EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUTTB_COUNT_DOWN
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm2Regs.TBCTL.bit.PHSDIR=TB_DOWN;
// EPwm2Regs.TBPHS.all=30000;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
// EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm2Regs.CMPA.half.CMPA = 30000;
EPwm2Regs.CMPB = 30000;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;
}
void epwm_init_2(void)
{
EPwm3Regs.TBPRD = 60000; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 60000;
EPwm3Regs.TBCTL.bit.PHSEN=1;
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBCTL.bit.SYNCOSEL=TB_SYNC_IN;
// EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUTTB_COUNT_DOWN
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm3Regs.TBCTL.bit.PHSDIR=TB_DOWN;
// EPwm2Regs.TBPHS.all=30000;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
// EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm3Regs.CMPA.half.CMPA = 30000;
EPwm3Regs.CMPB = 30000;
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
}
void epwm_init_3(void)
{
EPwm4Regs.TBPRD = 60000; // Set timer period
EPwm4Regs.TBPHS.half.TBPHS = 60000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUTTB_COUNT_DOWN
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm4Regs.TBCTL.bit.PHSDIR=TB_DOWN;
// EPwm2Regs.TBPHS.all=30000;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
// EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm4Regs.CMPA.half.CMPA = 30000;
// Set actions
EPwm4Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm4Regs.AQCTLB.bit.CAD = AQ_SET;
}
|
Stage
|
Commutation Logic
|
|||
|
Sensor Status
|
||||
|
A
|
B
|
D
|
||
|
S1
|
0
|
0
|
1
|
0
|
|
S2
|
0
|
0
|
1
|
1
|
|
S3
|
0
|
0
|
0
|
1
|
|
S4
|
1
|
0
|
0
|
1
|
|
S5
|
1
|
0
|
0
|
0
|
|
S6
|
1
|
1
|
0
|
0
|
|
S7
|
0
|
1
|
0
|
0
|
|
S8
|
0
|
1
|
1
|
0
|
|
S9
|
0
|
0
|
1
|
0
|
|
S10
|
0
|
0
|
1
|
1
|
| Stage | Commutation Logic | Energising Phase | ||||
| Sensor Status | ||||||
| A | B | C | D | Start | Run | |
| S1 | 0 | 0 | 1 | 0 | B | B |
| S2 | 0 | 0 | 1 | 1 | BA | A |
| S3 | 0 | 0 | 0 | 1 | A | A |
| S4 | 1 | 0 | 0 | 1 | AD | D |
| S5 | 1 | 0 | 0 | 0 | D | D |
| S6 | 1 | 1 | 0 | 0 | DC | C |
| S7 | 0 | 1 | 0 | 0 | C | C |
| S8 | 0 | 1 | 1 | 0 | CB | B |
| S9 | 0 | 0 | 1 | 0 | B | B |
| S10 | 0 | 0 | 1 | 1 | BA | A |