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TMS320F28069M XRS Pin self resetting

Other Parts Discussed in Thread: TMS320F28069M, TMS320F28069

hi guys, 

In our design we use the TMS320F28069M cpu with the internal oscillator (X1 tied to GND).

3.3v and 1.9v are looking fine (ripple < 15mV).

After the startup the XRS Pin is every 14ms going down for 50us and repeating.

The cpu is not programmed at all.

We have two board with exact the same problem.

It seems like the same problem:

http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/270397/946054.aspx

What can we do?

alex

  • Alex,

    This is the watchdog timer.  As you say, the CPU (i.e. flash) is not programmed at all.  Therefore, the device is running off the internal 10 MHz oscillator and the WD timeout is 13.11 ms (you said you observed 14 ms, so it matches).

    You should be able to connect with Code Composer Studio and flash the device.

    - David

  • Hi David,

    Thank you for your quick response.

    Our Main Problem is that we can't programmed the CPU with XDS100V2 and CCS6.

    Therefore we looked if we had some hardware issues.

    We thought the problem is the XRS that we can't programmed.

    But you say this is ok but I can't programmed the cpu when the cpu resets ? 

    We tried the xds100v2 and xds100v3 programmer.

    Alex

  • Alex,

    So you're saying you cannot CONNECT at all with JTAG (i.e., using CCS, you try to connect to the target), and that the flash has never been programmed?  I'm not talking about flashing the device.  Just try to CONNECt with CCSv6.

    What happens if you do a "Test Connection" from the Target Configuration page in CCSv6?  What is reported?

    If so, then it sounds like you have some sort of hardware problem on your board.  Does more than one board have this same problem?

    Regards,

    David

  • Hi David,

    Here are my Output from the Test Connection.

    We have 2 boards with the same Problem.

    I thought I can not connect to the Target because the XRS resets always my CPU.

    Regards,

    Alex

  • Alex,

    From the results you sent, the JTAG test is failing.  Since JTAG cannot connect and there is no code in the flash to disable the watchdog, the watchdog is resetting the device.  The reset is NOT why you cannot connect via JTAG.  The reset is being caused because you cannot connect.

    You said you have two boards like this.  This suggests other than a component level problem.  You may have something wrong with your board design.  Check your JTAG connections.  The header should look like this:

    although you do not have EMU0 and EMU1 on the F2806x so these would just be no connects on your board.

    Per the device datasheet sprs698e, Table 4-1, you normally should have a 2.2K pulldown on TRSTn.

    The device connections should look like this:

    If you have a second emulator, try that to rule out the emulator.  Alternately, if you have a TI EVM board, use the emulator to connect to that, again to rule out the emulator.

    Regards,

    David

  • David,

    Thanks for your response,

    Our connection is right.

    We proved it several times. We tried 2 programmer and 2 boards.

    Nothing works.

    Now we had done following test.

    With an spectrum Analyzer we analysed a Good Target connection between a Bad Target connection.

    JTAG Reset = yellow line, JTAG CLK = blue line.

    We found out that the JTAG Reset (yellow line)  goes low on startup on the Good Target.

    On the Bad Target connection, JTAG  Reset is still high.

    Our Good target is the ControlCard ISO TMS320F28069M.

    This can be our Problem but we don't why?.

    Is there another GPIO Pin that can be set the Target into an state that no JTAG programming is possible?.

     

    We now are very helpless,

    Alex,

    Archive.zip
  • >> Is there another GPIO Pin that can be set the Target into an state that no JTAG programming is possible?.

    The TDI, TDO, and TMS pins are shared with GPIO on F2806x devices.  But since you say the device has never been programmed, these pins should stay as JTAG function after a reset.  You can try rigging the bootmode pins so the device boot in 'Wait' mode (see datasheet SPRS698e, p.43).  This would keep any code in the device that re-configured the JTAG pins to GPIO from running.  I doubt very much however that this is the problem.

    I think you have a board level problem.  Check the continuity each each signal from the JTAG header to the device.  Make sure you can pull each signal high or low (i.e., make sure the line is not stuck).  Check the 3.3V power supply rail going to the F2806x.  Check the PD pin at the JTAG header.  It should be 3.3V.

    - David

     

  • Hi David,

    Thank you for your help.

    Now, we can program the CPU with the XDS100V3 . :-). But we don't know why :-(.

    I think also its an level problem, but the signals shows good.

    We tested serveral programmers.

    These programmers don't work with our board.

    2 x XDS100V2 programmers from spectrum.

    1 x XDS100V3 programmer from olimex.

    Now we buy another XDS100V3 programmer from spectrum and hope we can program.

    This is now the solution for us, but its not a good solution.

    Alex

  • Alex,

    Try slowing down the JTAG clock in CCS and see if that helps.  Modify the CCS target configuration:

    The default clock for xds100v2 and xds100v3 is 1 MHz (which is already pretty slow from the standard 10 MHz JTAG clock for XDS510 class emulators, but you never know).  I don't think this is going to help, but it is worth trying.

    - David

  • Hello,

    I am having the same problem, with a custom on-board xds100v2. I have attempted to put the device into wait mode, but it does not appear to go into wait mode. The TMS320F28069 continues to cycle the watch dog.

    The XRS pin on my board is isolated from all other circuits except a 2.2k pull-up.

    GPIO34 is pulled low (GND) through a 2.2K
    TDS is pulled high (3.3V) through a 2.2K

    Should the watchdog be enabled in this configuration?
  • Nicholas,

    yes the watchdog is enabled in wait boot mode. You can also try putting the device in SCI boot mode where it waits for the auto baud lock, however the SCITX and SCIRX pins used by SCIBOOT are pulled high in this boot mode.

    in wait boot mode you should be able to connect to JTAG in between watchdog resets.

    Best Regards

    Santosh