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Dual-edge PWM implementation with HV Kit

I want to implement dual-edge PWM in the HV kit. Is this as simple as changing the PWM registers in the f2803xileg_vdc.h file to: 

EPwm1Regs.ETSEL.bit.SOCASEL = 3; ?

Essentially I just want to double the sampling rate (synched to the peak and valley of the double update triangle), while keeping the switching frequency at the baseline 10 kHz (ISR_freq).

Any insight is appreciated.

Troy

  • Troy,

    This will double the ADC sample rate as you mention.  Only thing to look out for is to make sure the ISR time is small enough that you get out before the next(now in 1/2 time) INT comes from the ADC.

    Best,

    Matthew

  • Thanks Mathew,

    I was watching the loop time on a scope through a simple cycling of a GPIO pin. Increasing the rate still only took ~56% of the available time. I also updated the PWM counter compare module to update at at both ZRO and PRD, as simply updating the sample rate without updating the PWM compare would have minimal benefits (control loop still sees the previous sample rate).

    I did still see some odd behavior. This behavior being that when I scaled my control loop gains for the increased sampling and control rate, I had to turn off the integral gain on the Id loop. However, I left the Iq current loop alone and it worked fine. I know my controller gains are good as the are based on the tuned lower sample rate. This lead to me think I needed to update some other parameter in the configuration. Have you heard of any similar problems? I am using the ETSUN PMSM motor, which is non-salient, so it does not make sense to me that one of the current loops would be unstable and the other one works fine with the increased rate. They also work just fine with identical gains at the lower sampling and control rate.

    Troy