• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 82 subscribers
  • Views 4936 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Changing Interrupt Priority

Mehmet
Expert 1255 points

Selamunaleykum to everyone;

i am trying to change interrupt priority.
In my project, i am using " External Interrupt INT 1.4 " and  "SCI RX Interrupt INT 9.1"
Default, external interrupt priority higher than SCI RX interrupt priority. 

But i want to make SCI RX interrupt priority higher than external interrupt priority.

i need your help, to be succeed.

I am using  TMS320F28030 .

Thanks & regards from Türkiye

  • 0
    Guru 20525 points

    Hi,

    I hope this wiki link will help you.

    Regards,

    Igor

  • 0
    TI__Guru 61235 points

    Mehmet,

    Interrupt priority on C2000 devices applies only when more than one interrupt request is pending on the same cycle.  This is the hardware priority the governs that, and you cannot change that.  The general rule here is that any enabled interrupt that is pending (has its flag set) will immediately interrupt whatever routine you are in (again, provided all enable bits and masks are enabled between the interrupt and the CPU, including the INTM bit).  In your example, if you re-enable the INTM bit in the exernal INT 1.4, the SCI RX interrupt INT 9.1 will interrupt you there.  Similarly, do not re-enable interrupts in INT 9.1, and INT 1.4 will not interrupt you there.

    Igor pointed you to a decent Wiki site on interrupt prioritization.  This means you adjust the interrupt enables in an ISR, and then re-enable the INTM bit.  This allow only the interrupts you are interested in being able to interrupt that ISR.  I know there are also other posts on this topic on the forum.  You can search for them.

    Regards,

    David

  • 0 in reply to David M. Alter
    Expert 1255 points

    Thanks for replies, i searched forum but i could not find a solution for my problem.
    (maybe i found but i could not understand because i am newbie, unfortunately ) 

    my problem is;
    after external interrupt calculate ADC datas value, sci rx interrupt try to send this value to PC, when someone ask this value.
    BUT while sci is sending these values, another external interrupt occurs and i can not send these values  properly..

    so i try to re-enable INTM bit like David M. Alter said:
    I re-enabled INTM bit in the exernal INT 1.4, but the SCI RX interrupt INT 9.1 won't interrupt me there
    my code below

    __interrupt void xint1_isr(void)
    {
    GetAdcData();
    PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
    IER |= M_INT9;

    }


    __interrupt void SciRxInt(void)
    {
    rGetCommand[q]=SciaRegs.SCIRXBUF.bit.RXDT;
    q++;

    if(q>=3)
    {
    command=rGetCommand[0];
    command=command<<8;
    command=command+rGetCommand[1];
    command=command<<8;
    command=command+rGetCommand[2];

    if(command==0x7f0183)
    {
    sendADCdata();
    }
    q=0;
    }

    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=PIEACK_GROUP9; // Issue PIE ack
    }

  • 0 in reply to Igor Gorbachev
    Expert 1255 points

    Thanks Igor;

    I studied link which you gave me

    i try to change Global Priority  (INT 1.4 and INT 9.1)

    wiki link say that : This priority can be managed by manipulating the CPU IER register. 

    but i cannot find CPU IER register, so i cannot manipulate CPU IER register.

  • 0 in reply to Mehmet
    TI__Guru 71815 points

    Mehmet,

    IER is a CPU core register, and as such has been defined as a global var, such that you can manipulate it accordingly in C, ex:

    IER = 0x0000;

    or whatever you wish to do.

    I want to go back to what David is saying; once you are in an ISR, unless you explicitly re-enable interrupts they will not  be serviced until you return from the current ISR.


    Can you confirm that the issue you have is when the XINT and the SCI X-mit interrupts are coming at the same time?  You can handle this per the above posts, but it may be simpler to keep a FIFO in RAM and when the SCI X-mit is called you could see if there are multiple ADC results to scan out.

    If you are saying that the physical SCI X-mit is getting interrupted by the XINT then this shouldn't be possible unless you are explicitly enabling global interrupts in your ISR; ala CLRC INTM instruction(Clear the Interrupt Mask).  This is normally done by the ISR itself as part of the IRET assembly instruction.