F28335 McBSP in SPI Mode - clock duty cycle

Peter Fritzenschaft

Hi,

I´m using the McBSP A (GPIO20-23) in SPI Mode to connect a Serial MRAM.

Commissioning of my HW showed that the clock duty cycle (MCLKXA, GPIO22) is not 50/50, but the high/low phases are a multiple of LSPCLK cycle time (75MHz --> 13.33ns).

In our configuration with 25MHz SPI Clock, the duty cycle is 1xHigh/2xLow.

I could not find anything about this behaviour in the data Sheets (SPRS581D and SPRUFB7B).

Technical this is not a Problem, but I want to know if the low Phase of the clock is always the longer one when the baud rate has an odd divider to LSPCLK.

Regards, Peter Fritzenschaft

over 9 years ago

0 Vivek Singh over 9 years ago

TI__Guru** 109165 points

Hi Peter,

If the divider value is set to divide the clock by odd number then the duty cycle will not be 50/50 and which (low or high) pulse will be longer depends on the configuration of CLKXP bit in PCR register. If it's been configured to transmit data on rising edge of CLKX then HIGH pulse will be longer else LOW pulse will be longer.

Regards,

Vivek Singh