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F28M36 C28 rev0 flash prefetch problems without fast branching

I have the Advisory C28x Flash: The SBF and BF Instructions Will Not Execute From Flash for revision 0 taken into account, and compile libraries and code with the -me option. This way it is possible to run code on the C28 core with flash instruction prefetch enabled.

However, (minor) changes to the code sometimes do make the faulty behavior of unplugged interrupt exceptions reappear. In that case when stepping through the code at assembly level (showing that SBF nor BF are present) the exception does not occur. Disabling the instruction prefetch is another 'solution'.

So my question is, is there any other cause known of C28 instruction prefetch related issues in revision 0 F28M36 chips?

We are working on having a newer revision chip on our board, but till then we are struggling with a low speed limped dsp core.

  • Ernst,

    Did you program ECC for the application code in Flash using AutoEccGeneration option in Flash Plugin GUI?  If not, you will get ECC errors.  Did you check if there is any ECC error?

    What interrupt are you getting when you execute with prefetch enabled?  

    There is no any other known C28x Flash prefetch issue.

    Thanks and regards,

    Vamsi

          

  • Hello Vamsi,

    I program the Flash via CCS XDS100v2, with the Verify Flash after Program, and the Auto ECC Generation options checked; only necessary sectors are erased).

    I did not check the ECC registers while experiencing the problem; at the moment with prefetching disabled only the Test Data Out registers have a non-zero value.

    The interrupt that occurs is #19, illegal instruction.

    Given a set of 'faulty' code this always occurs at the same location, typically already during initialization, before BIOS_start(); and, as said, you can step through with no problem so there is not really an illegal instruction. When only clearing the prefetch enable in the boot phase, the same code runs with no problem.

    I use CCS 5.5 with TI-RTOS 1.20.

    Thanks for the reply. I now know that I did not miss another known issue. I hope to have an updated board with new revision chip soon, so digging deeper might not be needed. Otherwise, I could try to create a reproducable code set for the development kit for further investigation.

    Regards,

    Ernst

  • Ernst,

    Test data out registers are applicable only for ECC test mode.  You have to check ECC single bit error address register and double bit error address register.  However, you are saying that you programmed ECC using AutoECCGeneration mode.  Hence, I don't think it is a ECC issue.

    Please check whether you have the wait-states configured correctly or not.  Check in the memory window at the register address after you execute the instruction that sets the wait-state and make sure that the wait-states are properly initialized as required per frequency.  

    Also check to make sure that you have 7-Nops at the end of your Flash initialization routine which configures wait-states and cache/prefetch.  

    I noticed few BIOS users who modified the register headers and InitFlash function and failed to execute the code properly because of their modifications with respect to wait-states and Nops mentioned above.

    Anyways, you can check your code on the new board as well as you mentioned.

    Thanks and regards,

    Vamsi