Hello,
I'm going to be setting up a DMA from Xintf Zone to internal SRAM and was wondering what the speed would be. The XINTF Lead/Active/Trail is 1/3/0 using SYSCLKOUT/2 (75 MHz) or 8 SYSCLKOUT cycles. I looked at SPRUFB8D and it says the DMA Transfer has a delay of 4 SYSCLK Cycles (Figure 3). Is the total time to do the DMA Access 4 + (1 + 3)*2 =12 SYSCLKOUT cycles?
Or does the 2 cycle Read SRC N & Out SRC addr N in Figure 3 data get replaced by 8 cycles for the XINTF access and the total DMA time is 8 + 1 (Out DST addr) + 1 (Out SRC addr) = 10 SYSCLKOUT cycles?
Thanks,
Sha