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Questions about 28335 adc-dma

Yang tianxi
Intellectual 525 points

i want to achieve following actions on F28335:

1, sample ADC_INA0/AD/ADC_INB0, ADC_INA1/AD/ADC_INB simutaneously, each channel 2048 words respectively

2, the data are transfered to RAM via DAM

3, after a SOC pulse, the ADC converts the 4 channel data automatically, CPU doesn't intervene the ADC anymore

how to configure ADC registers and DAM regester?

My big doubts is that when ADC is configured as continuous mode, is it necessary to implent  SEQ1 interrupt  ISR,since SEQ1 goes back to CONV00 automatically.

can anyone who is familiar with F28335 ADC module help me? thanks a lot

  • 0
    TI__Guru 71605 points

    Yang,

    You want to use the SEQ_OVRD bit in ADCTRL1 along with CONT_RUN mode with the ADC set to cascaded sequencer.

    Then, set MAXCONV1 = 3, which should get you 4 double conversions for your A0/B0 and A1/B1.    Then you will duplicate the channels for RESULTS 8-15.  The interrupt will fire for every 8 results and you can use the DMA to transfer to your SRAM.


    ADC/DMA setup code is below:

       AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;        // 1 Cascaded Mode
   AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
   AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
   AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
   AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;
   AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x0;
   AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x1;
   AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x0;
   AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x1;
   AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x0;
   AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x1;
   AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3;   // Set up ADC to perform 4 conversions for every SOC
      
   AdcRegs.ADCTRL3.bit.SMODE_SEL = 1;// Enable Simultaneous Sampling
       AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1

   DMADest   = &DMABuf1[0];              //Point DMA destination to the beginning of the array
   DMASource = &AdcMirror.ADCRESULT0;    //Point DMA source to ADC result register base
   DMACH1AddrConfig(DMADest,DMASource);
   DMACH1BurstConfig(7,1,1);             //Transfer 8 results to RAM every burst
   DMACH1TransferConfig(255,1,1);        //Stop after 2048 words are sent((2048/8) - 1)
   DMACH1WrapConfig(1,0,2048,0);         //Every other burst reset the source pointer to ADCRESULT0  destination is >>than transfer size so never happens.
	  
    
  DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,SYNC_DISABLE,SYNC_SRC,
	                 OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);

  • 0 in reply to MatthewPate
    Intellectual 525 points

    thanks for your reply ,it's helpful