Hey all, I am trying to interface a PCM3002 to an F28335 via McBSP. My sample rates are being supplied by the ePWM of the F28335 and they are: LRCIN = 41.85 kHz, Bitclock = 1.33 MHz, and the sysclock = 10.75 Mhz. These values, hopefully, are close enough for normal operation of the PCM. I've gone through this guide,SPRA595,even though the device is different I figure the principles are identical. The main issue I'm having is no ISR's are triggering. I figure this has nothing to do with the PCM itself so I disconnect that device and fed the ePWM signals straight to the McBSP B pins. Still, no ISR's are triggering. Below is my initialization code for my ePWM and McBSPB.
Code critique is always welcome, thanks in advance to anyone who takes the time to go through this.
InitSysCtrl(); EALLOW; InitEPwm5Gpio(); InitEPwm4Gpio(); InitEPwm6Gpio(); EALLOW; SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
// Setup SYSCLK EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up EPwm5Regs.TBPRD =7 ; // Set timer period EPwm5Regs.TBCTR = 0x0000; // Clear counter EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0x0; // Clock ratio to SYSCLKOUT EPwm5Regs.TBCTL.bit.CLKDIV = 0x0; // Setup BitCLK EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up EPwm4Regs.TBPRD =56 ; // Set timer period EPwm4Regs.TBCTR = 0x0000; // Clear counter EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x0; // Clock ratio to SYSCLKOUT EPwm4Regs.TBCTL.bit.CLKDIV = 0x0; // Setup LRCIn EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up EPwm6Regs.TBPRD = 1792 ; // Set timer period EPwm6Regs.TBCTR = 0x0000; // Clear counter EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0x0; // Clock ratio to SYSCLKOUT EPwm6Regs.TBCTL.bit.CLKDIV = 0x0; // Setup shadow register load on ZERO EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Set Compare values EPwm6Regs.CMPA.half.CMPA = 896; // Set compare A value EPwm5Regs.CMPA.half.CMPA = 3; // Set compare A value EPwm4Regs.CMPA.half.CMPA = 28; // Set compare A value // Set Actions EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; EPwm6Regs.AQCTLA.bit.CAD = AQ_CLEAR; EPwm5Regs.AQCTLA.bit.CAU = AQ_SET; EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR; EPwm4Regs.AQCTLA.bit.CAU = AQ_SET; EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR; SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; //Reset Codec GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0; GpioCtrlRegs.GPADIR.bit.GPIO14 = 1; GpioDataRegs.GPADAT.bit.GPIO14 = 0; DELAY_US(1000); GpioDataRegs.GPADAT.bit.GPIO14 = 1; InitMcbspbGpio(); //Recieve Registers McbspbRegs.RCR1.bit.RWDLEN1 = 0x2; //16 bit word McbspbRegs.RCR2.bit.RPHASE = 0x1; //Dual-phase frame McbspbRegs.RCR1.bit.RFRLEN1 = 0x0; //1 word in phase1; McbspbRegs.RCR2.bit.RFRLEN2 = 0x0; //1 word in phase2 McbspbRegs.RCR2.bit.RCOMPAND = 0x0; //No companding McbspbRegs.RCR2.bit.RDATDLY = 0x0; //0 clock data-delay //Transmit Registers McbspbRegs.XCR1.bit.XWDLEN1 = 0x2; //16 bit word McbspbRegs.XCR2.bit.XPHASE = 0x1; //Dual-phase frame McbspbRegs.XCR1.bit.XFRLEN1 = 0x0; //1 word in phase1; McbspbRegs.XCR2.bit.XFRLEN2 = 0x0; //1 word in phase2 McbspbRegs.XCR2.bit.XCOMPAND = 0x0; //No companding McbspbRegs.XCR2.bit.XDATDLY = 0x0; //0 clock data-delay //Pin Configuration McbspbRegs.PCR.bit.FSXM = 0; //Transmit frame-sync generated externally McbspbRegs.PCR.bit.FSRM = 0; //Recieve frame-sync generated externally McbspbRegs.PCR.bit.CLKXM = 0; //Transmit clock is generated externally McbspbRegs.PCR.bit.CLKRM = 0; //Receive clock is generated externally McbspbRegs.PCR.bit.SCLKME = 1; //MCLKX is used McbspbRegs.SRGR2.bit.CLKSM = 1; //MCLKX is used McbspbRegs.PCR.bit.FSXP = 0; //Active high transmit frame-sync pulse McbspbRegs.PCR.bit.FSRP = 0; //Active high recive frame-sync pulse McbspbRegs.PCR.bit.CLKXP = 0; //Data is clocked out on the rising edge of SCK McbspbRegs.PCR.bit.CLKRP = 0; //Data is sampled in on the falling edge of SCK
//************ Enable TX/RX unit McbspbRegs.SPCR2.bit.XRST=1; McbspbRegs.SPCR1.bit.RRST=1; InitPieCtrl(); IER = 0x0000; IFR = 0x0000; InitPieVectTable(); EALLOW; PieVectTable.MRINTB = &Mcbspb_rx_isr; PieVectTable.MRINTB = &Mcbspb_tx_isr; McbspbRegs.MFFINT.bit.RINT = 1; // Enable Receive Interrupts PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block PieCtrlRegs.PIEIER6.bit.INTx3=1; // Enable PIE Group 6, INT 3 PieCtrlRegs.PIEIER6.bit.INTx4=1; // Enable PIE Group 6, INT 4 IER |= M_INT6; // Enable CPU INT6 EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM