Hello All,
I am using TMS320F28069 with AD1938.
I am using the McBSP along with DMA to get the TDM8 data from AD1938 & sent back after processing.
The AD1938 is configured as Master & the lines CLKX, FSX, CLKR and FSR are driven by AD1938.
The data received on the McBSP port looks random when I dump & plot the data.
Could any one confirm the if the Initialisation of McBSP is fine?
Data is 24-bit format with 32 BCLK from AD1938.
void McBSP_init (void)
{
/*************** RESET MCBSP ****************/
McbspaRegs.SPCR2.bit.FRST = 0; // Frame Sync generator reset
McbspaRegs.SPCR2.bit.GRST = 0; // Sample Rate generator Reset
McbspaRegs.SPCR2.bit.XRST = 0; // Transmitter reset
McbspaRegs.SPCR1.bit.RRST = 0; // Receiver reset
/****************************************************************************************************************/
// Receiver Configuration
// Global Behaviour
McbspaRegs.SPCR1.bit.DLB = 0; // digital loop back disabled
McbspaRegs.SPCR1.bit.CLKSTP = 0; // clock stop mode disabled
McbspaRegs.MCR1.bit.RMCM = 1; // Enable Receive multichannel selection mode
McbspaRegs.MCR1.bit.RMCME = 0; // 2-partition mode
McbspaRegs.MCR1.bit.RPBBLK = 0; // Block 1 : channels 16 to 31 is assigned to B partition
McbspaRegs.MCR1.bit.RPABLK = 0; // Block 0 : channels 0 to 15 is assigned to A partition
McbspaRegs.RCERA.all = 0; // initially disable all the channels
McbspaRegs.RCERB.all = 0; // initially disable all the channels
McbspaRegs.RCERA.bit.RCEA0 = 1; // enable channel 1
McbspaRegs.RCERA.bit.RCEA1 = 1; // enable channel 2
McbspaRegs.RCERA.bit.RCEA2 = 1; // enable channel 3
McbspaRegs.RCERA.bit.RCEA3 = 1; // enable channel 4
McbspaRegs.RCERA.bit.RCEA4 = 1; // enable channel 5
McbspaRegs.RCERA.bit.RCEA5 = 1; // enable channel 6
McbspaRegs.RCERA.bit.RCEA6 = 1; // enable channel 7
McbspaRegs.RCERA.bit.RCEA7 = 1; // enable channel 8
// Data Behaviour
McbspaRegs.RCR2.bit.RPHASE = 0; // single phase frame
McbspaRegs.RCR1.bit.RWDLEN1 = 0x5; // word length = 32bit
McbspaRegs.RCR1.bit.RFRLEN1 = 7; // 8 word per frame
McbspaRegs.RCR2.bit.RFIG = 1; // ignores unexpected receive frame sync pulses
McbspaRegs.RCR2.bit.RCOMPAND = 0; // No Companding
McbspaRegs.RCR2.bit.RDATDLY = 1; // 1-bit data delay
McbspaRegs.SPCR1.bit.RJUST = 0; // Right justify the data and sign-extend the data into the MSBs
McbspaRegs.SPCR1.bit.RINTM = 0; // RINT generated when RRDY changes from 0 to 1.
// Frame-synchronization behaviour
McbspaRegs.PCR.bit.FSRM = 0; // Receive frame synchronization is supplied externally
McbspaRegs.PCR.bit.FSRP = 0; // Frame-synchronization pulse FSR is active high.
//Clock Behaviour
McbspaRegs.PCR.bit.CLKRM = 0; // Internal CLKX is driven externally
McbspaRegs.PCR.bit.CLKRP = 0; // Receive data is sampled on the falling edge of MCLKR.
//Clock Synchronization Mode
McbspaRegs.SRGR2.bit.GSYNC = 1; // Clock synchronization is performed. When a pulse is detected on the FSR pin
McbspaRegs.PCR.bit.SCLKME = 1; // Sample rate generator clock derived from MCLKR pin
McbspaRegs.SRGR2.bit.CLKSM = 0;
/****************************************************************************************************************/
//Transmitter Configuration
McbspaRegs.MCR2.bit.XMCM = 1; // Enable transmitter multichannel selection mode
McbspaRegs.MCR2.bit.XMCME = 0; // 2-partition mode
McbspaRegs.MCR2.bit.XPBBLK = 0; // Block 1 : channels 16 to 31 is assigned to B partition
McbspaRegs.MCR2.bit.XPABLK = 0; // Block 0 : channels 0 to 15 is assigned to A partition
McbspaRegs.XCERA.all = 0; // initially disable all the channels
McbspaRegs.XCERB.all = 0; // initially disable all the channels
McbspaRegs.XCERA.bit.XCERA0 = 1; // enable channel 1
McbspaRegs.XCERA.bit.XCERA1 = 1; // enable channel 2
McbspaRegs.XCERA.bit.XCERA2 = 1; // enable channel 3
McbspaRegs.XCERA.bit.XCERA3 = 1; // enable channel 4
McbspaRegs.XCERA.bit.XCERA4 = 1; // enable channel 5
McbspaRegs.XCERA.bit.XCERA5 = 1; // enable channel 6
McbspaRegs.XCERA.bit.XCERA6 = 1; // enable channel 7
McbspaRegs.XCERA.bit.XCERA7 = 1; // enable channel 8
// Data Behaviour
McbspaRegs.XCR2.bit.XPHASE = 0; // Single-phase frame
McbspaRegs.XCR1.bit.XWDLEN1 = 5; // Transmit word length is 32 bits
McbspaRegs.XCR1.bit.XFRLEN1 = 7; // 8 word per frame
McbspaRegs.XCR2.bit.XFIG = 1; // ignores unexpected transmit frame sync pulses
McbspaRegs.XCR2.bit.XCOMPAND = 0; // No companding, any size data, MSB transmitted first
McbspaRegs.XCR2.bit.XDATDLY = 1; // 1-bit data delay
McbspaRegs.SPCR1.bit.DXENA = 0; // DX delay enabler is off.
McbspaRegs.SPCR2.bit.XINTM = 0; // XINT generated when XRDY changes from 0 to 1.
// Frame-synchronization behaviour
McbspaRegs.PCR.bit.FSXM = 0; // Transmit frame synchronization is externally
McbspaRegs.SRGR2.bit.FSGM = 1; // The transmitter uses frame-sync pulses generated by SRC. Program the FWID bits to
// set the width of each pulse. Program the FPER bits to set the frame-synchronization period
McbspaRegs.PCR.bit.FSXP = 0; // Frame-synchronization pulse FSX is active high.
//Clock Behaviour
McbspaRegs.PCR.bit.CLKXM = 0; // Internal CLKX is driven externally
// The MCLKR pin is an output pin that reflects internal MCLKR.
McbspaRegs.PCR.bit.CLKXP = 1; // Transmit data sampled on falling edge of CLKX
/****************************************************************************************************************/
// McBSP Interrupt Enable Register
McbspaRegs.MFFINT.all = 0;
//McbspaRegs.MFFINT.bit.XINT = 1; // Enable Transmit Interrupts
//McbspaRegs.MFFINT.bit.RINT = 1; // Enable Receive Interrupts
// Immediate stop mode (reset condition)
// The transmitter or receiver stops immediately in response to a breakpoint & completing current transfer
McbspaRegs.SPCR2.bit.FREE = 0;
McbspaRegs.SPCR2.bit.SOFT = 1;
//************* Enable Sample rate generator
McbspaRegs.SPCR2.bit.GRST = 0;
delay_loop(); // Wait at least 2 SRG clock cycles
//************ Frame Sync generator reset
McbspaRegs.SPCR2.bit.FRST = 0;
delay_loop(); // Wait at least 2 SRG clock cycles
//************ Enable TX/RX unit
McbspaRegs.SPCR2.bit.XRST = 1; // The serial port transmitter is enabled.
McbspaRegs.SPCR1.bit.RRST = 1; // The serial port receiver is enabled.
}
