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sdfm TMS320F2837x

Tjarco Boerkoel
Expert 1725 points
Other Parts Discussed in Thread: ADS1203, ADS1209, ADS1274

Hi All,

I'm trying to get some feeling with the buildin SDFM filter. I connected a delta sigma ADC with modulator output to a SDFM input and let it convert continuously resulting in a nice 25MHz datastream. The datafilter is setup with OSR (128-1), SINC3, 32bit date representation and is enabled. Now I read data from the filter data register.

in the datasheet is written: The data filter uses 25 bits to represent signed integer in two's complement format. The maximum
possible resolution gives a 25-bit word (-16,777,216 to +16,777,215). Note that this value is only reached
if the delta-sigma modulator is operated at absolute maximum positive or negative full-scale...

Well, what if I'm using a 8-bit converter and go to an absolute positive input? Is the filter data output then also represented in a 25bit word with a stepsize of 256 steps?

Or how do I have to see this? Could someone help me understand the SDFM module and its resolution? The datasheet is a bit brief.

best regards,

Tjarco

  • 0
    TI__Guru 55700 points

    Tjarco,

    SDFM filter input pins expect receive 1-BIT sigma delta modulated bit stream. Is your modulated output from your SD ADC a 1 bit SD modulated o/p?

    Example of SD modulator which can be used with SDFM filter:-

    http://www.ti.com/product/ads1203

    http://www.ti.com/product/ads1209

    Have you already reviewed SDFM section in TRM? It provides lot more information about SDFM than datasheet.

    Regards,

    Manoj

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Expert 1725 points

    Hi Manoj.


    Thank you for your reply. Yes, sorry the TRM was the document I referred to.

    The ADC I currently have connected is an ADS1274 @ 25MHz clkock source resulting in a bitstream clocked out at 6.25MHz.
     The SDFM input has been configured as MODULATOR MODE 0, is asynchr input and the clock input GPIO has inverter enabled. The filter has been configured as 32bit OSR=127 , SINC3 and shift=0. Sync and interrupt options are disabled.

    The inputs of the ADC are connected to its own VCM output and buffered with capacitance.

    I see a lot of variation between conversions results. Have I misconfigured something?

    Best regards

  • 0 in reply to Tjarco Boerkoel
    TI__Guru 55700 points

    Tjarco,

    Your SDFM filter settings seems to be fine. I'm not quite sure about your SD modulator settings. I believe following questions will help you get the settings right:-

    1. Did you make sure to configure data output format to give out modulated output?
    2. Did you check both modulated data and clock from modulator using oscilloscope?
    3. SDFM MODE0, strobes for data at every rising edge. Is SD modulator also providing data and clock to be strobed in rising edge?

    Based on Table 14. Data output format from ADS1274 datasheet, you need to have format[0] = 0, format[1] = format[2] = 1 to enter modulator mode.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Expert 1725 points

    H Manoj,

    Thank you for you support. Yes the Format[2:0] is setup as you suggested and the ADC is generating a nice modulation stream. The ADC is clocking out on risingg edge, so I have configured the GPIO for the clock input as inverting. This seems to be working. If I 'powerdown' the ADC channel, the filter data is not updated. If I re-enable the ADC channel it continuous conversion. So I think this working to.

    If I apply an voltage to the ADC, the ADC value changes corresponding to the changes of the applied voltage. That seems to work.

    But I'm not getting a 24bit result in the SDFM filter data register, it seems to be lower than the ADCs 24bit resolution. The maximum and minimum values in the filter data register are around +/-2,000,000. O, I think I'm seeing some light here now.

    When I take a look at the filter characteristics than the maximum and minimum filter values, with Sinc3 and OSR=128, would be +/-2,097,152 and that corresponds with the filter register. So, correct me if I'm wrong, if I would have a 24bit result I have to increase the filter OSR to be between OSR=128 and OSR=256?

    When OSR=128, does the data filter need 128 new 'bits' or is (or can be) this a fifo with continuous conversion (or updated after OSR/2 cycles)? It's a continuous stream so it would be nice if I don't have to wait for OSR-amount of new bits to receive.

    [Edit] I see quite some variation on the filter value, always +/- 100 decimal code spread. Is this normal?

    Best regards,

    Tjarco