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F28377D NDAT_X and NDAT_21 regs

Other Parts Discussed in Thread: TMS320F28377D, CONTROLSUITE

Hi All,


I am looking at a design using the CAN peripheral on a TMS320F28377D. I am polling a mailbox to see if data has been received and thought I could use the CAN_NDAT_21 and CAN_NDAT_X regs to see when a new message has arrived. However I cannot see the mechanism that clears these bits.

All I can find in the datasheet is a reference to them being cleared by the CPU (they are read only) but no mechanism for this.

I have also looked at the example code from ControlSuite and the bits never seem to get cleared in there either.

Can anyone point me at the right documentation or give me an example of how these bits are cleared?

Many thanks,

Adam


Edit: I tried doing the same thing using the IF3 registers but hit the same problem. I set the IF3UPD register to auto update the IF3 data from the correct mailbox. This works fine but again I do not see how to reset the NewDat bit!?

SPRUHM8B says that

"The NewDat bit in the message object will be reset by a transfer to IF3."

Can anyone explain to me what this means?

Many thanks,

Adam