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TMS320F28335 SCI Rx FIFO Interrupt Occur-ing without Data Transmitted on the Line From other TMS320F28335 Evaluation Board

lakshmi komali
Intellectual 515 points
Other Parts Discussed in Thread: TMS320F28335, MAX232

Hai all,

I have an EZDSP F28335 Evaluation Board(B1) configured for SCI RX Interrupt for a FIFO level of 9-bits.

Another TMS320F28335 Peripheral Explorer(B2) is Flash programmed to Transmit 18-bits of data every 1ms on SCI.

B1 and B2 both are TTL level(not connected through MAX232).

Initially, B2 is Off.

When B1 is On, and It should wait to receive Data and should not generate Interrupt till B2 is Switched On. But B1 is getting SCI Rx Interrupt is when B2 is in Off condition(Garbage Data on line).

When B2 is switched On, then B1 is getting the expected data. and again if B2 is Off, B1 is not getting Interrupts(no garbage data on Line). Initially also the same behavior is expected as we are giving it to Client and we don't know the initial condition of other side of B1.

 

Please help me with resolving : What may be the issue Hardware/Software?

If I want this to solve in Software, which way I can do? I can't put a condition to check few bytes as SCI RX interrupt is the highest Priority Interrupt, and it will stay in the same loop not giving time to other processes.

EDITED:

I have referred the link, have the same problem explained in this. But Can't use the Flag based as my SCI Rx data is high priority, and should be updated immediately whenever available without fail.

http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/366616.aspx

Thankyou,

Lakshmi Komali.

  • 0
    TI__Guru 71835 points

    Lakshmi,

    Along the lines of the linked post, can we check the validity of the received data in the ISR and just throw it out if it is garbage?  Is there CPU BW problem using this method?

    Matt

  • 0 in reply to MatthewPate
    Intellectual 515 points

    Hai Matt,

    Thankyou for your response.

    We are checking after all 18-bytes are received using a flag, so that ISR(Highest Priority) is not occupying more CPU time. If we check the validity of the received data in every ISR, atleast 3 conditions are required, which is causing CPU BW problem.

    Lakshmi Komali 

  • 0 in reply to lakshmi komali
    Mastermind 7585 points

    There is probably something wrong in your software setup of SCI-FIFO. If you set the Interrupt for SCI-RX-FIFO to 9, then the Interrupt will be triggered only if 9 or more characters have been received.

    What is the status of the error-bits, when you can the unexpected Interrupts?

    What is the level of the Rx-line, while your 2nd node is not active? Is it floating, or is it stable at '1'?

     

  • 0 in reply to Frank Bormann
    Intellectual 515 points

    Hai Frank,

    Thankyou for your response.

    I have set the Interrupt for SCI-RX-FIFO to 9, and the Interrupt is triggered for every 9 or more characters have been received. But the received 9-bytes are junk data (like 0x0007 or 0x8000 for all 9-bytes).

    Unexpected Interrupts are generated only when other device is connected to Rx and Tx pins, otherwise SCI RX FIFO INTR is not triggering.

    Error bits are not set as it is receiving 9-bytes as data.

     Rx-line is low while 2nd node is not active.

     

    Thankyou,

    Lakshmi Komali.