Shared RAM not working for passing data between cores on F28M35x

Michael He

Other Parts Discussed in Thread: CONTROLSUITE

I'm having trouble passing data between the cores via shared ram on the F28M35H52C1.

I've followed the examples shown in Ram Management and Lab 5, implemented basically the same lines, but when I run the code, I do not see the values actually getting updated at the target core. For example, the C28 writes a value of 3.1415 into the variable, but the corresponding variable on the M3 remains 0, its initial value.

Here are the relevant parts of the code. Am I missing something?

C28 main:

#pragma DATA_SECTION("SHARERAMS2");
float c28_r_array;     // mapped to S2 of shared RAM owned by M3
#pragma DATA_SECTION("SHARERAMS0");
float c28_r_w_array;   // mapped to S0 of shared RAM owned by c28


void main(void)
{
   ......
   c28_r_w_array = 3.1415;
   ......
}

C28 linker:

  RAMS0       : origin = 0x00C000, length = 0x001000     /* on-chip Shared RAM block S0 */
   RAMS1       : origin = 0x00D000, length = 0x001000     /* on-chip Shared RAM block S1 */
   RAMS2       : origin = 0x00E000, length = 0x001000     /* on-chip Shared RAM block S2 */
   RAMS3       : origin = 0x00F000, length = 0x001000     /* on-chip Shared RAM block S3 */
   RAMS4       : origin = 0x010000, length = 0x001000     /* on-chip Shared RAM block S4 */
   RAMS5       : origin = 0x011000, length = 0x001000     /* on-chip Shared RAM block S5 */
   RAMS6       : origin = 0x012000, length = 0x001000     /* on-chip Shared RAM block S6 */

......

   SHARERAMS0          : > RAMS0,        PAGE = 1
   SHARERAMS1          : > RAMS1,        PAGE = 1
   SHARERAMS2          : > RAMS2,        PAGE = 1
   SHARERAMS3          : > RAMS3,        PAGE = 1
   SHARERAMS4          : > RAMS4,        PAGE = 1
   SHARERAMS5          : > RAMS5,        PAGE = 1
   SHARERAMS6          : > RAMS6,        PAGE = 1

M3 main:

#pragma DATA_SECTION("SHARERAMS0");
float m3_r_array; // this array is mapped to S0

#pragma DATA_SECTION("SHARERAMS2");
float m3_r_w_array; // this array is mapped to S2


void main(void)
{
   ......
   RAMMReqSharedMemAccess((S0_ACCESS),C28_MASTER);
   ......
}

M3 linker:

S0 (RWX)        : origin = 0x20010000, length = 0x2000
    S1 (RWX)        : origin = 0x20012000, length = 0x2000
    S2 (RWX)        : origin = 0x20014000, length = 0x2000
    S3 (RWX)        : origin = 0x20016000, length = 0x2000
    S4 (RWX)        : origin = 0x20018000, length = 0x2000
    S5 (RWX)        : origin = 0x2001A000, length = 0x2000
    S6 (RWX)        : origin = 0x2001C000, length = 0x2000
    S7 (RWX)        : origin = 0x2001E000, length = 0x2000


.......

SHARERAMS0  : > S0
    SHARERAMS1  : > S1
    SHARERAMS2  : > S2
    SHARERAMS3  : > S3
    SHARERAMS4  : > S4
    SHARERAMS5  : > S5
    SHARERAMS6  : > S6
    SHARERAMS7  : > S7

I also tried very similar code shown in Lab5, using the CtoM and MtoC, but that does not work either.

Am I misunderstanding something? All I should need to do is to link the memory, then link with the pragma, then set or read the variables, correct? (FYI I am programming in C++ so the pragma syntax is slightly different. Also I tried changed the arrays from the example to be single variables for testing, but it does not work either way)

Thanks for any help!

over 9 years ago

0 Michael He over 9 years ago

Expert 2170 points

I just did more testing and I made a mistake on the CtoM version. Therefore, the CtoM/MtoC version from Lab5 is working, but the SharedRAM version still does not work. The code seems functionally identical in both cases, so what am I missing here?

Copied below is the relevant code for the CtoM/MtoC version. I don't see how it is different from the SharedRAM version.

M3 code:

#pragma DATA_SECTION("CtoM")
unsigned int AdcValue = 0;

M3 linker:

    CTOMRAM (RX)    : origin = 0x2007F000, length = 0x0800
    MTOCRAM (RWX)   : origin = 0x2007F800, length = 0x0800

CtoM: > CTOMRAM, TYPE = DSECT

C28 code:

#pragma DATA_SECTION("CtoM")
Uint16 LatestADCResult;

C28 linker:

   CTOMRAM     : origin = 0x03F800, length = 0x000380     
   MTOCRAM     : origin = 0x03FC00, length = 0x000380     

CtoM : > CTOMRAM, PAGE = 1

0 Michael He over 9 years ago in reply to Michael He

Expert 2170 points

Hello,

Any suggestions on this issue?

Thanks

0 Michael He over 9 years ago in reply to Michael He

Expert 2170 points

Sorry to bump this again, but hoping somebody can help with this issue. I've been using the CtoM RAM now, and that works fine, but will probably need to use the SharedRam soon. I don't understand why one works and the other doesn't. I haven't been able to find a solution in the TRM or this forum.

0 Noah:Berhanu over 9 years ago in reply to Michael He

TI__Intellectual 2795 points

The shared RAM region is owned by M3 at reset. You have to invoke the RAMMReqSharedMemAccess() function with the appropriate masks. The RAM_management example makes use of this function. Please refer to the RAM_management example in controlSUITE.

Thanks

Noah

0 Michael He over 9 years ago in reply to Noah:Berhanu

Expert 2170 points

I do invoke RAMMReqSharedMemAccess. See the code I posted in the original post, copied below:

RAMMReqSharedMemAccess((S0_ACCESS | S1_ACCESS),C28_MASTER);

0 Noah:Berhanu over 9 years ago in reply to Michael He

TI__Intellectual 2795 points

Lets do one step at a time then. Does the RAM_management example work for you as is (without any modification)?

Thanks

Noah

0 Michael He over 9 years ago in reply to Noah:Berhanu

Expert 2170 points

The RAM_management project does not work, in the sense that there are problems with the project itself. I imported the project from controlSuite, but I get the following two errors without any further explanation:

Description Resource Path Location Type
.ccsproject /RAM_management_C28 line 74, external location: C:\ti\controlSUITE\device_support\f28m35x\v204\F28M35x_common\cmd\F28M35x_generic_wshared_C28_FLASH.cmd C/C++ Problem

Description Resource Path Location Type
errors encountered during linking; "RAM_management_c28.out" not built RAM_management_C28 C/C++ Problem

The error does not point me anywhere in the code. I have not been able to fix the error, hence I am copying the relevant code to my own project to test.

I have studied the example though, and copied what I saw to be the relevant code into my own project. I posted that code in my initial post. As far as I understand, that should be sufficient to use the Shared RAM between cores.

0 Noah:Berhanu over 9 years ago in reply to Michael He

TI__Intellectual 2795 points

Hi Michael,

indeed there is a bug in the command linker file.

Please delete line 74 in F28M35x_generic_wshared_C28_FLASH.cmd file and replace it with

RAMM0 : origin = 0x0000A1, length = 0x00035F /* on-chip RAM block M0 */

I tested the code with the above fix and with the below code showing the relevant changes.

M3 side:

float c28_f_r_array[4]; // this array is mapped to S1

#pragma DATA_SECTION(c28_f_r_w_array,"SHARERAMS1");

int main (void)

{

// Other Code

test = c28_f_r_w_array[0];

while(1) ;

}

C28x Side:

float c28_f_r_w_array[4]; // mapped t0 S1 of shared RAM owned by C28x

#pragma DATA_SECTION(c28_f_r_w_array,"SHARERAMS1");

void main(void)

{

// Other code

c28_f_r_w_array[0] = 2.345f;

// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;){}
}

Let me know if you still have issues.

Thanks

Noah

0 Michael He over 9 years ago in reply to Noah:Berhanu

Expert 2170 points

Hi Noah,

That fixed the issue! Thank you very much!

A quick question: Can you point me to a reference or guide on how to change memory allocation sizes as needed? I'm finding for example that lwip requires a lot of space in .bss, more than what fits in the 0x2000 in the default allocation.

Thanks

Mike

0 Michael He over 9 years ago in reply to Michael He

Expert 2170 points

To clarify, I'm not asking how to edit the linker file itself. I've been running with an edited linker file to accommodate lwip for a while now. What I'm asking is how to do it "right". I've just been somewhat arbitrarily increasing the size of certain sections as needed, but I don't know if what I'm doing is safe or good practice. I don't know if I might mess something up.

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Shared RAM not working for passing data between cores on F28M35x