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f2837xD watchdog timer reset

Hi All , 

I am trying to implement a watchdog timer which resets the device. 

When running the program , 

The watchdog counter WDCNTR overflows, but the WDFlag gets set and then immediately resets itself , instead of waiting for me the clear the WDFlag .The program then continues running .  I am not servicing the watchdog. Could you tell me what I am missing ? 

#include "F28x_Project.h"     // Device Headerfile and Examples Include File

long int LoopCount = 0;

void main(void)
{

//   unsigned long delay;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
    InitSysCtrl();

// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
    DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
    InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
    InitPieVectTable();


// Step 4. Initialize all the Device Peripherals:
// This function is found in F2837xD_InitPeripherals.c
// InitPeripherals(); // Not required for this example

// Connect the watchdog to the WAKEINT interrupt of the PIE
// Write to the whole SCSR register to avoid clearing WDOVERRIDE bit
	EALLOW;

	WdRegs.SCSR.all = 0;
	EDIS;

	EINT;                                // Enable Global Interrupts

// Reset the watchdog counter
	ServiceDog();

		// Enable the watchdog
		EALLOW;
		WdRegs.WDCR.all = 0x0028;
		EDIS;


// Step 6. IDLE loop. Just sit and loop forever (optional):
    for(;;)
    {
        LoopCount++;
//         ServiceDog();
    }
}

  • Hi Anish,

    On this device we have another register by name "RESC" (2.13.10.25 RESC Register (offset = 80h) [reset = 3h])which has status flag "WDRSn" to indicates if reset was caused by watchdog. I would recomend to use this flag. Let me know if this works.

    Regards,

    Vivek Singh 

  • Anish,

    In this device, watchdog module can be used to reset the device (or) generate watchdog interrupt depending upon SCSR[WDENINT].

    If SCSR[WDENINT] = 0 (default condition), watchdog will generate a device reset

    If SCSR[WDENINT] = 1, watchdog generate watchdog interrupt and doesn't generate device reset

    So, if you wish to generate watchdog interrupt, you can need to have SCSR[WDENINT] = 1. This should allow you to  clear the flag etc in WD_ISR routine.

    Regards,

    Manoj

  • Hi Vivek,

    I was able to use the RESC register to verify the reset. Thanks. 

    Could you help me with  the following scenario: 

    I am servicing the watchdog in CPU1 . I  have used the same program above for CPU2 . When the watchdog timer in CPU2 overflows , the  CpuSysRegs.RESC.bit.WDRSn  flag gets set to '1' and CPU2 stops running . 

    I am able to reset CPU1 core by using the CPU2WDRSn flag . Please tell me how to restart CPU2  too after CPU1 is reset . 

    Changes made in F2837xD_DefaultISR.c : 

    // Non-Maskable Interrupt
    interrupt void NMI_ISR(void)
    {
        // Insert ISR Code here
    
        // Next two lines for debug only to halt the processor here
        // Remove after inserting ISR Code
    		
    			asm ("      ESTOP0");
    			for(;;);
    }

    CPU1 code : 

    #include "F28x_Project.h"     // Device Headerfile and Examples Include File
    
    
    long int LoopCount = 0;
    
    void main(void)
    {
    
        InitSysCtrl();
    
            InitGpio(); // Skipped for this example
            EALLOW;
            GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
            GPIO_SetupPinOptions(34, GPIO_OUTPUT, GPIO_PUSHPULL);
            GPIO_SetupPinMux(34, GPIO_MUX_CPU2, 0);
            //TODO Add code to allow configuration of GPADIR from CPU02 using IPC
            EDIS;

     DELAY_US(1000 * 250); GpioDataRegs.GPADAT.bit.GPIO31 = 1;// turn off LED DINT; InitPieCtrl(); // Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000; InitPieVectTable(); EALLOW; WdRegs.SCSR.all = 0; EDIS; EINT; // Enable Global Interrupts // Reset the watchdog counter ServiceDog(); if(CpuSysRegs.RESC.bit.WDRSn == 1) { //count++; EALLOW; WdRegs.WDCR.all = 0x00A8; CpuSysRegs.RESC.bit.WDRSn = 1; DevCfgRegs.CPU2RESCTL.bit.RESET = 1; //Reset CPU2 (dont think i need this) EDIS; } else { // Enable the watchdog EALLOW; WdRegs.WDCR.all = 0x0028; EDIS; } LoopCount = 0; // Step 6. IDLE loop. Just sit and loop forever (optional): for(;;) { ServiceDog(); } }

    CPU2 code : 

    #include "F28x_Project.h"     // Device Headerfile and Examples Include File
    
    
    
    long int LoopCount2 = 0;
    
    void main(void)
    {
    
        InitSysCtrl();

    GPIO_WritePin(34, 1); //LED off
    DINT; InitPieCtrl(); IER = 0x0000; IFR = 0x0000; InitPieVectTable(); EALLOW; WdRegs.SCSR.all = 0; EDIS; EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM // Reset the watchdog counter ServiceDog(); if(CpuSysRegs.RESC.bit.WDRSn == 1) { EALLOW; WdRegs.WDCR.all = 0x00A8; CpuSysRegs.RESC.bit.WDRSn = 1; EDIS; } else { // Enable the watchdog EALLOW; WdRegs.WDCR.all = 0x0028; EDIS; } // Step 6. IDLE loop. Just sit and loop forever (optional): for(;;) { LoopCount2++; //ServiceDog(); } }

    Regards

    Anish

  • Hi Anish,

    After CPU2 WD triggers reset for CPU2, CPU2 should start running after reset for CPU2 get de-asserted (done in hardware). So I didn't under stand what you mean by "CPU2 stops running".  Is it going into ITRAP?

    I hope you are running this code from Flash. Please confirm.

    In your CPU1 code, you have following line.

    DevCfgRegs.CPU2RESCTL.bit.RESET = 1;   //Reset CPU2 (dont think i need this)

    This is not correct for two reasons. Ist, to write this field, you also need to write to KEY field else this field cannot be written. IInd, writing '1' to this bit will held  CPU2 in RESET (it's not auto clear bit) and one need to write '0' to this bit to release CPU2 from reset.

    Since CPU2 reset get's release in CPU1 BOOT-ROM (which will run after WD reset) hence user need not to do this in their code.

    Regards,

    Vivek Singh

  • Hi Vivek , 

    I had to add a delay of DELAY_US(250000) in CPU2 after InitSysCtrl();

    Else the CPU2 goes to ESTOP. 

    Yes the code was running from Standalone Flash . 

    The problem is solved now.

    Regards

    Anish

  • Hi Anish,

    On this device CPU1 is master and have the ownership of most of the resources at start-up. If CPU2 tries to access any of these resources before CPU1 assign them to CPU2, there will be issue. For example all the global shared RAMs (GSx RAMs) are owned by CPU1 and if CPU2 tries to execute code from any of GSx RAM before CPU1 release the ownership to CPU2, CPU2 will ITRAP and code will stuck into ESTOP (if user has not defined ITRAP routine).

    Good that this issue is resolved by adding delay in CPU2 code. You could also use the IPC routines to communicate between CPU1 & CPU2 so that CPU2 start execution of application code only after CPU1 is done with system initialization.

    Regards,

    Vivek Singh

     

  • Hello borther , my name is Duc and I am a reseacher from Ulsan university korea. Now I change from 28335 to 28377D . I just want to use one core (only CPU1) and program in flash. However , there is no example in control suite ( example adc_pwm or soc_pwm , blinky_cpu1 I tranfer to Ram is ok. But I dont know how to tranfer to flash. Its not like 28335 where we have init_flash() and memcopy.

    I try many way but have prolem in : 1) build project (from example )
    2) EStop0 when using flash ( like CPU1 going to freeze when init flash or interrupt)
    Do u have any " small project " that can debug to DSP. Please help me . I use Jtag 100V2 to program to DSP

    Thank u so much