Hello everyone,
I have a program where every recessive-to-dominant edge is delayed by a number of time quanta equal to my SJW value, as if the eCAN was resynchronizing with itself.
The delay between the TX and the RX lines is slightly longer than 200ns.
The weird thing is that I always see the problem when the board is power-cycled, but never when I load the program using the JTAG emulator and run it directly from CCS using the "CPU reset" button.
How is the initialization by the JTAG different from when the program is starting from Flash ? Does it do anything to the eCAN registers ?
I'm currently out of ideas :(
Pierre